自学教程：C++ ARM_CPU函数代码示例

static void pxa262_initfn(Object *obj){    ARMCPU *cpu = ARM_CPU(obj);    set_feature(&cpu->env, ARM_FEATURE_V5);    set_feature(&cpu->env, ARM_FEATURE_XSCALE);    cpu->midr = 0x69052d06;    cpu->ctr = 0xd172172;    cpu->reset_sctlr = 0x00000078;}

static void ti925t_initfn(Object *obj){    ARMCPU *cpu = ARM_CPU(obj);    set_feature(&cpu->env, ARM_FEATURE_V4T);    set_feature(&cpu->env, ARM_FEATURE_OMAPCP);    cpu->midr = ARM_CPUID_TI925T;    cpu->ctr = 0x5109149;    cpu->reset_sctlr = 0x00000070;}

static void smdkc210_init(MachineState *machine){    Exynos4210State *s = exynos4_boards_init_common(machine,                                                    EXYNOS4_BOARD_SMDKC210);    lan9215_init(SMDK_LAN9118_BASE_ADDR,            qemu_irq_invert(s->irq_table[exynos4210_get_irq(37, 1)]));    arm_load_kernel(ARM_CPU(first_cpu), &exynos4_board_binfo);}

/* MADT */static voidbuild_madt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info){    int madt_start = table_data->len;    const MemMapEntry *memmap = guest_info->memmap;    const int *irqmap = guest_info->irqmap;    AcpiMultipleApicTable *madt;    AcpiMadtGenericDistributor *gicd;    AcpiMadtGenericMsiFrame *gic_msi;    int i;    madt = acpi_data_push(table_data, sizeof *madt);    gicd = acpi_data_push(table_data, sizeof *gicd);    gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR;    gicd->length = sizeof(*gicd);    gicd->base_address = memmap[VIRT_GIC_DIST].base;    for (i = 0; i < guest_info->smp_cpus; i++) {        AcpiMadtGenericInterrupt *gicc = acpi_data_push(table_data,                                         sizeof *gicc);        ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));        gicc->type = ACPI_APIC_GENERIC_INTERRUPT;        gicc->length = sizeof(*gicc);        if (guest_info->gic_version == 2) {            gicc->base_address = memmap[VIRT_GIC_CPU].base;        }        gicc->cpu_interface_number = i;        gicc->arm_mpidr = armcpu->mp_affinity;        gicc->uid = i;        gicc->flags = cpu_to_le32(ACPI_GICC_ENABLED);    }    if (guest_info->gic_version == 3) {        AcpiMadtGenericRedistributor *gicr = acpi_data_push(table_data,                                             sizeof *gicr);        gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR;        gicr->length = sizeof(*gicr);        gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST].base);        gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST].size);    } else {        gic_msi = acpi_data_push(table_data, sizeof *gic_msi);        gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME;        gic_msi->length = sizeof(*gic_msi);        gic_msi->gic_msi_frame_id = 0;        gic_msi->base_address = cpu_to_le64(memmap[VIRT_GIC_V2M].base);        gic_msi->flags = cpu_to_le32(1);        gic_msi->spi_count = cpu_to_le16(NUM_GICV2M_SPIS);        gic_msi->spi_base = cpu_to_le16(irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE);    }    build_header(linker, table_data,                 (void *)(table_data->data + madt_start), "APIC",                 table_data->len - madt_start, 3, NULL);}

const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname){    ARMCPU *cpu = ARM_CPU(cs);    if (strcmp(xmlname, "system-registers.xml") == 0) {        return cpu->dyn_xml.desc;    }    return NULL;}

static void cortex_a9_initfn(Object *obj){    ARMCPU *cpu = ARM_CPU(obj);    set_feature(&cpu->env, ARM_FEATURE_V7);    set_feature(&cpu->env, ARM_FEATURE_VFP3);    set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);    set_feature(&cpu->env, ARM_FEATURE_NEON);    set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);    /* Note that A9 supports the MP extensions even for     * A9UP and single-core A9MP (which are both different     * and valid configurations; we don't model A9UP).     */    set_feature(&cpu->env, ARM_FEATURE_V7MP);    cpu->midr = 0x410fc090;    cpu->reset_fpsid = 0x41033090;    cpu->mvfr0 = 0x11110222;    cpu->mvfr1 = 0x01111111;    cpu->ctr = 0x80038003;    cpu->reset_sctlr = 0x00c50078;    cpu->id_pfr0 = 0x1031;    cpu->id_pfr1 = 0x11;    cpu->id_dfr0 = 0x000;    cpu->id_afr0 = 0;    cpu->id_mmfr0 = 0x00100103;    cpu->id_mmfr1 = 0x20000000;    cpu->id_mmfr2 = 0x01230000;    cpu->id_mmfr3 = 0x00002111;    cpu->id_isar0 = 0x00101111;    cpu->id_isar1 = 0x13112111;    cpu->id_isar2 = 0x21232041;    cpu->id_isar3 = 0x11112131;    cpu->id_isar4 = 0x00111142;    cpu->clidr = (1 << 27) | (1 << 24) | 3;    cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */    cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */    {        ARMCPRegInfo cbar = {            .name = "CBAR", .cp = 15, .crn = 15,  .crm = 0, .opc1 = 4,            .opc2 = 0, .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,            .fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address)        };        define_one_arm_cp_reg(cpu, &cbar);        define_arm_cp_regs(cpu, cortexa9_cp_reginfo);    }}#ifndef CONFIG_USER_ONLYstatic int a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri,                           uint64_t *value){    /* Linux wants the number of processors from here.     * Might as well set the interrupt-controller bit too.     */    *value = ((smp_cpus - 1) << 24) | (1 << 23);    return 0;}

static void arm946_initfn(Object *obj){    ARMCPU *cpu = ARM_CPU(obj);    set_feature(&cpu->env, ARM_FEATURE_V5);    set_feature(&cpu->env, ARM_FEATURE_MPU);    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);    cpu->midr = 0x41059461;    cpu->ctr = 0x0f004006;    cpu->reset_sctlr = 0x00000078;}

static bool arm_cpu_has_work(CPUState *cs){    ARMCPU *cpu = ARM_CPU(cs);    return !cpu->powered_off        && cs->interrupt_request &        (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD         | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ         | CPU_INTERRUPT_EXITTB);}

static void sa1100_initfn(Object *obj){    ARMCPU *cpu = ARM_CPU(obj);    cpu->dtb_compatible = "intel,sa1100";    set_feature(&cpu->env, ARM_FEATURE_STRONGARM);    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);    cpu->midr = 0x4401A11B;    cpu->reset_sctlr = 0x00000070;}

static void pxa261_initfn(Object *obj){    ARMCPU *cpu = ARM_CPU(obj);    cpu->dtb_compatible = "marvell,xscale";    set_feature(&cpu->env, ARM_FEATURE_V5);    set_feature(&cpu->env, ARM_FEATURE_XSCALE);    cpu->midr = 0x69052d05;    cpu->ctr = 0xd172172;    cpu->reset_sctlr = 0x00000078;}

static void aarch64_a53_initfn(Object *obj){    ARMCPU *cpu = ARM_CPU(obj);    cpu->dtb_compatible = "arm,cortex-a53";    set_feature(&cpu->env, ARM_FEATURE_V8);    set_feature(&cpu->env, ARM_FEATURE_VFP4);    set_feature(&cpu->env, ARM_FEATURE_NEON);    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);    set_feature(&cpu->env, ARM_FEATURE_AARCH64);    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);    set_feature(&cpu->env, ARM_FEATURE_EL2);    set_feature(&cpu->env, ARM_FEATURE_EL3);    set_feature(&cpu->env, ARM_FEATURE_PMU);    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;    cpu->midr = 0x410fd034;    cpu->revidr = 0x00000000;    cpu->reset_fpsid = 0x41034070;    cpu->isar.mvfr0 = 0x10110222;    cpu->isar.mvfr1 = 0x12111111;    cpu->isar.mvfr2 = 0x00000043;    cpu->ctr = 0x84448004; /* L1Ip = VIPT */    cpu->reset_sctlr = 0x00c50838;    cpu->id_pfr0 = 0x00000131;    cpu->id_pfr1 = 0x00011011;    cpu->id_dfr0 = 0x03010066;    cpu->id_afr0 = 0x00000000;    cpu->id_mmfr0 = 0x10101105;    cpu->id_mmfr1 = 0x40000000;    cpu->id_mmfr2 = 0x01260000;    cpu->id_mmfr3 = 0x02102211;    cpu->isar.id_isar0 = 0x02101110;    cpu->isar.id_isar1 = 0x13112111;    cpu->isar.id_isar2 = 0x21232042;    cpu->isar.id_isar3 = 0x01112131;    cpu->isar.id_isar4 = 0x00011142;    cpu->isar.id_isar5 = 0x00011121;    cpu->isar.id_isar6 = 0;    cpu->isar.id_aa64pfr0 = 0x00002222;    cpu->id_aa64dfr0 = 0x10305106;    cpu->isar.id_aa64isar0 = 0x00011120;    cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */    cpu->dbgdidr = 0x3516d000;    cpu->clidr = 0x0a200023;    cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */    cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */    cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */    cpu->dcz_blocksize = 4; /* 64 bytes */    cpu->gic_num_lrs = 4;    cpu->gic_vpribits = 5;    cpu->gic_vprebits = 5;    define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);}

static uc_err arm_query(struct uc_struct *uc, uc_query_type type, size_t *result){    CPUState *mycpu = first_cpu;    switch(type) {        case UC_QUERY_MODE:            *result = (ARM_CPU(uc, mycpu)->env.thumb != 0);            return UC_ERR_OK;        default:            return UC_ERR_ARG;    }}

static void arm_any_initfn(Object *obj){    ARMCPU *cpu = ARM_CPU(obj);    set_feature(&cpu->env, ARM_FEATURE_V8);    set_feature(&cpu->env, ARM_FEATURE_VFP4);    set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);    set_feature(&cpu->env, ARM_FEATURE_NEON);    set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);    set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);    set_feature(&cpu->env, ARM_FEATURE_V7MP);    cpu->midr = 0xffffffff;}

static void arm926_initfn(Object *obj){    ARMCPU *cpu = ARM_CPU(obj);    set_feature(&cpu->env, ARM_FEATURE_V5);    set_feature(&cpu->env, ARM_FEATURE_VFP);    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);    set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);    cpu->midr = 0x41069265;    cpu->reset_fpsid = 0x41011090;    cpu->ctr = 0x1dd20d2;    cpu->reset_sctlr = 0x00090078;}

static void aarch64_any_initfn(Object *obj){    ARMCPU *cpu = ARM_CPU(obj);    set_feature(&cpu->env, ARM_FEATURE_V8);    set_feature(&cpu->env, ARM_FEATURE_VFP4);    set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);    set_feature(&cpu->env, ARM_FEATURE_NEON);    set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);    set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);    set_feature(&cpu->env, ARM_FEATURE_V7MP);    set_feature(&cpu->env, ARM_FEATURE_AARCH64);}

static void arm_any_initfn(Object *obj){    ARMCPU *cpu = ARM_CPU(obj);    set_feature(&cpu->env, ARM_FEATURE_V8);    set_feature(&cpu->env, ARM_FEATURE_VFP4);    set_feature(&cpu->env, ARM_FEATURE_NEON);    set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);    set_feature(&cpu->env, ARM_FEATURE_V8_AES);    set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);    set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);    set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);    set_feature(&cpu->env, ARM_FEATURE_CRC);    cpu->midr = 0xffffffff;}

static void cortex_m0plus_initfn(Object *obj){    ARMCPU *cpu = ARM_CPU(obj);    set_feature(&cpu->env, ARM_FEATURE_VAPA);    set_feature(&cpu->env, ARM_FEATURE_THUMB2);    set_feature(&cpu->env, ARM_FEATURE_MPIDR);    set_feature(&cpu->env, ARM_FEATURE_V6);    set_feature(&cpu->env, ARM_FEATURE_V5);    set_feature(&cpu->env, ARM_FEATURE_V4T);    set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV);    set_feature(&cpu->env, ARM_FEATURE_M0);    set_feature(&cpu->env, ARM_FEATURE_M0PLUS);    cpu->midr = 0x00000002;}

static void arm_cpu_post_init(Object *obj){    ARMCPU *cpu = ARM_CPU(obj);    if (arm_feature(&cpu->env, ARM_FEATURE_CBAR)) {        qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,                                 &error_abort);    }    if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {        qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,                                 &error_abort);    }}

static void aarch64_cpu_set_pc(CPUState *cs, vaddr value){    CPUARMState *env = cs->env_ptr;    ARMCPU *cpu = ARM_CPU(env->uc, cs);    /* It's OK to look at env for the current mode here, because it's     * never possible for an AArch64 TB to chain to an AArch32 TB.     * (Otherwise we would need to use synchronize_from_tb instead.)     */    if (is_a64(&cpu->env)) {        cpu->env.pc = value;    } else {        cpu->env.regs[15] = value;    }}

static void aarch64_a57_initfn(struct uc_struct *uc, Object *obj, void *opaque){    ARMCPU *cpu = ARM_CPU(uc, obj);    set_feature(&cpu->env, ARM_FEATURE_V8);    set_feature(&cpu->env, ARM_FEATURE_VFP4);    set_feature(&cpu->env, ARM_FEATURE_NEON);    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);    set_feature(&cpu->env, ARM_FEATURE_AARCH64);    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);    set_feature(&cpu->env, ARM_FEATURE_V8_AES);    set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);    set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);    set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);    set_feature(&cpu->env, ARM_FEATURE_CRC);    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;    cpu->midr = 0x411fd070;    cpu->reset_fpsid = 0x41034070;    cpu->mvfr0 = 0x10110222;    cpu->mvfr1 = 0x12111111;    cpu->mvfr2 = 0x00000043;    cpu->ctr = 0x8444c004;    cpu->reset_sctlr = 0x00c50838;    cpu->id_pfr0 = 0x00000131;    cpu->id_pfr1 = 0x00011011;    cpu->id_dfr0 = 0x03010066;    cpu->id_afr0 = 0x00000000;    cpu->id_mmfr0 = 0x10101105;    cpu->id_mmfr1 = 0x40000000;    cpu->id_mmfr2 = 0x01260000;    cpu->id_mmfr3 = 0x02102211;    cpu->id_isar0 = 0x02101110;    cpu->id_isar1 = 0x13112111;    cpu->id_isar2 = 0x21232042;    cpu->id_isar3 = 0x01112131;    cpu->id_isar4 = 0x00011142;    cpu->id_isar5 = 0x00011121;    cpu->id_aa64pfr0 = 0x00002222;    cpu->id_aa64dfr0 = 0x10305106;    cpu->id_aa64isar0 = 0x00011120;    cpu->id_aa64mmfr0 = 0x00001124;    cpu->dbgdidr = 0x3516d000;    cpu->clidr = 0x0a200023;    cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */    cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */    cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */    cpu->dcz_blocksize = 4; /* 64 bytes */    define_arm_cp_regs(cpu, cortexa57_cp_reginfo);}

int aarch64_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n){    ARMCPU *cpu = ARM_CPU(cs);    CPUARMState *env = &cpu->env;#ifndef CONFIG_USER_ONLY    if (!is_a64(env)) {        map_a32_to_a64_regs(env);    }#endif    if (n < 31) {        /* Core integer register.  */        return gdb_get_reg64(mem_buf, env->xregs[n]);    }    switch (n) {    case 31:    {        unsigned int cur_el = arm_current_el(env);        uint64_t sp;        aarch64_save_sp(env, cur_el);        switch (env->debug_ctx) {            case DEBUG_EL0:                sp = env->sp_el[0];                break;            case DEBUG_EL1:                sp = env->sp_el[1];                break;            case DEBUG_EL2:                sp = env->sp_el[2];                break;            case DEBUG_EL3:                sp = env->sp_el[3];                break;            default:                sp = env->xregs[31];                break;        }        return gdb_get_reg64(mem_buf, sp);    }    case 32:        return gdb_get_reg64(mem_buf, env->pc);    case 33:        return gdb_get_reg32(mem_buf, pstate_read(env));    }    /* Unknown register.  */    return 0;}

static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name,                               void *opaque, Error **errp){    ARMCPU *cpu = ARM_CPU(obj);    Error *err = NULL;    visit_type_uint32(v, name, &cpu->sve_max_vq, &err);    if (!err && (cpu->sve_max_vq == 0 || cpu->sve_max_vq > ARM_MAX_VQ)) {        error_setg(&err, "unsupported SVE vector length");        error_append_hint(&err, "Valid sve-max-vq in range [1-%d]/n",                          ARM_MAX_VQ);    }    error_propagate(errp, err);}

static void arm_any_initfn(Object *obj){    ARMCPU *cpu = ARM_CPU(obj);    set_feature(&cpu->env, ARM_FEATURE_V8);    set_feature(&cpu->env, ARM_FEATURE_VFP4);    set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);    set_feature(&cpu->env, ARM_FEATURE_NEON);    set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);    set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);    set_feature(&cpu->env, ARM_FEATURE_V7MP);    set_feature(&cpu->env, ARM_FEATURE_CRC);#ifdef TARGET_AARCH64    set_feature(&cpu->env, ARM_FEATURE_AARCH64);#endif    cpu->midr = 0xffffffff;}

static void arm_cpu_initfn(Object *obj){    CPUState *cs = CPU(obj);    ARMCPU *cpu = ARM_CPU(obj);    static bool inited;    cs->env_ptr = &cpu->env;    cpu_exec_init(&cpu->env);    cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,                                         g_free, g_free);    if (tcg_enabled() && !inited) {        inited = true;        arm_translate_init();    }}

static void aarch64_any_initfn(struct uc_struct *uc, Object *obj, void *opaque){    ARMCPU *cpu = ARM_CPU(uc, obj);    set_feature(&cpu->env, ARM_FEATURE_V8);    set_feature(&cpu->env, ARM_FEATURE_VFP4);    set_feature(&cpu->env, ARM_FEATURE_NEON);    set_feature(&cpu->env, ARM_FEATURE_AARCH64);    set_feature(&cpu->env, ARM_FEATURE_V8_AES);    set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);    set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);    set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);    set_feature(&cpu->env, ARM_FEATURE_CRC);    cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */    cpu->dcz_blocksize = 7; /*  512 bytes */}

static uc_err arm_query(struct uc_struct *uc, uc_query_type type, size_t *result){    CPUState *mycpu = first_cpu;    uint32_t mode;    switch(type) {        case UC_QUERY_MODE:            // zero out ARM/THUMB mode            mode = uc->mode & ~(UC_MODE_ARM | UC_MODE_THUMB);            // THUMB mode or ARM MOde            mode += ((ARM_CPU(uc, mycpu)->env.thumb != 0)? UC_MODE_THUMB : UC_MODE_ARM);            *result = mode;            return UC_ERR_OK;        default:            return UC_ERR_ARG;    }}

int arm_gen_dynamic_xml(CPUState *cs){    ARMCPU *cpu = ARM_CPU(cs);    GString *s = g_string_new(NULL);    RegisterSysregXmlParam param = {cs, s};    cpu->dyn_xml.num_cpregs = 0;    cpu->dyn_xml.cpregs_keys = g_malloc(sizeof(uint32_t *) *                                        g_hash_table_size(cpu->cp_regs));    g_string_printf(s, "<?xml version=/"1.0/"?>");    g_string_append_printf(s, "<!DOCTYPE target SYSTEM /"gdb-target.dtd/">");    g_string_append_printf(s, "<feature name=/"org.qemu.gdb.arm.sys.regs/">");    g_hash_table_foreach(cpu->cp_regs, arm_register_sysreg_for_xml, &param);    g_string_append_printf(s, "</feature>");    cpu->dyn_xml.desc = g_string_free(s, false);    return cpu->dyn_xml.num_cpregs;}

static void cortex_a15_initfn(Object *obj){    ARMCPU *cpu = ARM_CPU(obj);    cpu->dtb_compatible = "arm,cortex-a15";    set_feature(&cpu->env, ARM_FEATURE_V7);    set_feature(&cpu->env, ARM_FEATURE_VFP4);    set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);    set_feature(&cpu->env, ARM_FEATURE_NEON);    set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);    set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);    set_feature(&cpu->env, ARM_FEATURE_CBAR);    set_feature(&cpu->env, ARM_FEATURE_LPAE);    set_feature(&cpu->env, ARM_FEATURE_TRUSTZONE);    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;    cpu->midr = 0x412fc0f1;    cpu->reset_fpsid = 0x410430f0;    cpu->mvfr0 = 0x10110222;    cpu->mvfr1 = 0x11111111;    cpu->ctr = 0x8444c004;    cpu->reset_sctlr = 0x00c50078;    cpu->id_pfr0 = 0x00001131;    cpu->id_pfr1 = 0x00011011;    cpu->id_dfr0 = 0x02010555;    cpu->id_afr0 = 0x00000000;    cpu->id_mmfr0 = 0x10201105;    cpu->id_mmfr1 = 0x20000000;    cpu->id_mmfr2 = 0x01240000;    cpu->id_mmfr3 = 0x02102211;    cpu->id_isar0 = 0x02101110;    cpu->id_isar1 = 0x13112111;    cpu->id_isar2 = 0x21232041;    cpu->id_isar3 = 0x11112131;    cpu->id_isar4 = 0x10011142;    cpu->clidr = 0x0a200023;    cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */    cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */    cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */    define_arm_cp_regs(cpu, cortexa15_cp_reginfo);}

CPUState *arm_get_cpu_by_id(uint64_t id){    CPUState *cpu;    DPRINTF("cpu %" PRId64 "/n", id);    CPU_FOREACH(cpu) {        ARMCPU *armcpu = ARM_CPU(cpu);        if (armcpu->mp_affinity == id) {            return cpu;        }    }    qemu_log_mask(LOG_GUEST_ERROR,                  "[ARM]%s: Requesting unknown CPU %" PRId64 "/n",                  __func__, id);    return NULL;}

int aarch64_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n){    ARMCPU *cpu = ARM_CPU(cs);    CPUARMState *env = &cpu->env;    if (n < 31) {        /* Core integer register.  */        return gdb_get_reg64(mem_buf, env->xregs[n]);    }    switch (n) {    case 31:        return gdb_get_reg64(mem_buf, env->xregs[31]);    case 32:        return gdb_get_reg64(mem_buf, env->pc);    case 33:        return gdb_get_reg32(mem_buf, pstate_read(env));    }    /* Unknown register.  */    return 0;}