自学教程：C++ ASSERT0函数代码示例

//Record new region and delete it when RegionMgr destroy.void RegionMgr::addToRegionTab(Region * ru){    ASSERT(REGION_id(ru) > 0, ("should generate new region via newRegion()"));    ASSERT0(get_region(REGION_id(ru)) == NULL);    ASSERT0(REGION_id(ru) < m_ru_count);    m_id2ru.set(REGION_id(ru), ru);}

//All global prs must be mapped.bool DexRegion::verifyRAresult(RA & ra, Prno2Vreg & prno2v){    GltMgr * gltm = ra.get_gltm();    Vector<GLT*> * gltv = gltm->get_gltvec();    for (UINT i = 0; i < gltm->get_num_of_glt(); i++) {        GLT * g = gltv->get(i);        if (g == NULL) { continue; }        ASSERT0(g->has_allocated());        if (GLT_bbs(g) == NULL) {            //parameter may be have no occ.            continue;        }        bool find;        prno2v.get(GLT_prno(g), &find);        ASSERT0(find);    }    BBList * bbl = getBBList();    for (IRBB * bb = bbl->get_head(); bb != NULL; bb = bbl->get_next()) {        LTMgr * ltm = gltm->map_bb2ltm(bb);        if (ltm == NULL) { continue; }        Vector<LT*> * lvec = ltm->get_lt_vec();        for (INT i = 0; i <= lvec->get_last_idx(); i++) {            LT * l = lvec->get(i);            if (l == NULL) { continue; }            ASSERT0(l->has_allocated());            bool find;            prno2v.get(LT_prno(l), &find);            ASSERT0(find);        }    }    return true;}

voiddsl_dir_destroy_sync(void *arg1, void *tag, dmu_tx_t *tx){	dsl_dir_t *dd = arg1;	objset_t *mos = dd->dd_pool->dp_meta_objset;	uint64_t obj;	dd_used_t t;	ASSERT(RW_WRITE_HELD(&dd->dd_pool->dp_config_rwlock));	ASSERT(dd->dd_phys->dd_head_dataset_obj == 0);	/*	 * Remove our reservation. The impl() routine avoids setting the	 * actual property, which would require the (already destroyed) ds.	 */	dsl_dir_set_reservation_sync_impl(dd, 0, tx);	ASSERT0(dd->dd_phys->dd_used_bytes);	ASSERT0(dd->dd_phys->dd_reserved);	for (t = 0; t < DD_USED_NUM; t++)		ASSERT0(dd->dd_phys->dd_used_breakdown[t]);	VERIFY(0 == zap_destroy(mos, dd->dd_phys->dd_child_dir_zapobj, tx));	VERIFY(0 == zap_destroy(mos, dd->dd_phys->dd_props_zapobj, tx));	VERIFY(0 == dsl_deleg_destroy(mos, dd->dd_phys->dd_deleg_zapobj, tx));	VERIFY(0 == zap_remove(mos,	    dd->dd_parent->dd_phys->dd_child_dir_zapobj, dd->dd_myname, tx));	obj = dd->dd_object;	dsl_dir_close(dd, tag);	VERIFY(0 == dmu_object_free(mos, obj, tx));}

void DexRegion::processSimply(){    LOG("DexRegion::processSimply %s", getRegionName());    if (getIRList() == NULL) { return ; }    OptCtx oc;    OC_show_comp_time(oc) = g_show_comp_time;    CHAR const* ru_name = getRegionName();    constructIRBBlist();    ASSERT0(verifyIRandBB(getBBList(), this));    //All IRs have been moved to each IRBB.    setIRList(NULL);    PassMgr * passmgr = initPassMgr();    ASSERT0(passmgr);    ASSERT0(g_cst_bb_list);    IR_CFG * cfg = (IR_CFG*)passmgr->registerPass(PASS_CFG);    ASSERT0(cfg);    cfg->initCfg(oc);    ASSERT0(g_do_cfg_dom);    cfg->LoopAnalysis(oc);    destroyPassMgr();    //Do not allocate register.    getPrno2Vreg()->clean();    getPrno2Vreg()->copy(*getDex2IR()->getPR2Vreg());    return;}

    //Add left child    void add_rc(int from, RBCOL f, int to, RBCOL t)    {        TN * x = m_root;        if (x == NULL) {            m_root = new_tn(from, f);            x = new_tn(to, t);            m_root->rchild = x;            x->parent = m_root;            return;        }        List<TN*> lst;        lst.append_tail(x);        while (lst.get_elem_count() != 0) {            x = lst.remove_head();            if (x->key == from) {                break;            }            if (x->rchild != NULL) {                lst.append_tail(x->rchild);            }            if (x->lchild != NULL) {                lst.append_tail(x->lchild);            }        }        ASSERT0(x);        ASSERT0(x->color == f);        TN * y = new_tn(to, t);        ASSERT0(x->rchild == NULL);        x->rchild = y;        y->parent = x;    }

bool DexRegion::HighProcess(OptCtx & oc){    CHAR const* ru_name = getRegionName();    g_indent = 0;    SimpCtx simp;    SIMP_if(&simp) = true;    SIMP_doloop(&simp) = true;    SIMP_dowhile(&simp) = true;    SIMP_whiledo(&simp) = true;    SIMP_switch(&simp) = false;    SIMP_break(&simp) = true;    SIMP_continue(&simp) = true;    setIRList(simplifyStmtList(getIRList(), &simp));    ASSERT0(verify_simp(getIRList(), simp));    ASSERT0(verify_irs(getIRList(), NULL, this));    constructIRBBlist();    ASSERT0(verifyIRandBB(getBBList(), this));    //All IRs have been moved to each IRBB.    setIRList(NULL);    HighProcessImpl(oc);    return true;}

AbsNode * CfsMgr::constructAbsLoop(        IN IRBB * entry,        IN AbsNode * parent,        IN BitSet * cur_region,        IN Graph & cur_graph,        IN OUT BitSet & visited){    DUMMYUSE(cur_region);    ASSERT0(cur_region == NULL || cur_region->is_contain(BB_id(entry)));    IR_CFG * cfg = m_ru->getCFG();    LI<IRBB> * li = cfg->mapBB2LabelInfo(entry);    ASSERT0(li != NULL && LI_loop_head(li) == entry);    AbsNode * node = new_abs_node(ABS_LOOP);    set_map_bb2abs(entry, node);    ABS_NODE_parent(node) = parent;    ABS_NODE_loop_head(node) = entry;    IRBB * body_start;    cfg->getKidOfLoop(entry, NULL, &body_start);    ASSERT0(body_start != NULL);    CFS_INFO * ci = map_ir2cfsinfo(cfg->get_last_xr(entry));    CHECK_DUMMYUSE(ci);    ASSERT0(CFS_INFO_head(ci) == entry);    ASSERT0(CFS_INFO_loop_body(ci)->is_contain(*LI_bb_set(li)));    BitSet loc_visited;    ABS_NODE_loop_body(node) = constructAbsTree(body_start, node,        LI_bb_set(li), cur_graph, loc_visited);    visited.bunion(loc_visited);    visited.bunion(BB_id(entry));    return node;}

void DexRegion::updateRAresult(IN RA & ra, OUT Prno2Vreg & prno2v){    prno2v.maxreg = ra.get_maxreg();    prno2v.paramnum = ra.get_paramnum();    GltMgr * gltm = ra.get_gltm();    BBList * bbl = getBBList();    prno2v.clean();    for (IRBB * bb = bbl->get_head(); bb != NULL; bb = bbl->get_next()) {        LTMgr * ltm = gltm->map_bb2ltm(bb);        if (ltm == NULL) { continue; }        Vector<LT*> * lvec = ltm->get_lt_vec();        for (INT i = 0; i <= lvec->get_last_idx(); i++) {            LT * l = lvec->get(i);            if (l == NULL) { continue; }            ASSERT0(l->has_allocated());            bool find;            UINT v = prno2v.get(LT_prno(l), &find);            if (find) {                //each prno is corresponding to a unqiue vreg.                ASSERT0(v == LT_phy(l));            } else {                prno2v.set(LT_prno(l), LT_phy(l));            }        }    }    //prno2v.dump();    ASSERT0(verifyRAresult(ra, prno2v));}

//Allocate VMD and ensure it is unique according to 'version' and 'mdid'.VMD * UseDefMgr::allocVMD(UINT mdid, UINT version){    ASSERT0(mdid > 0);    Vector<VMD*> * vec = m_map_md2vmd.get(mdid);    if (vec == NULL) {        vec = new Vector<VMD*>();        m_map_md2vmd.set(mdid, vec);    }    VMD * v = vec->get(version);    if (v != NULL) {        return v;    }    ASSERT(m_vmd_pool, ("not init"));    v = (VMD*)smpoolMallocConstSize(sizeof(VMD), m_vmd_pool);    ASSERT0(v);    ::memset(v, 0, sizeof(VMD));    v->init(m_ru->getMiscBitSetMgr()->getSegMgr());    VOPND_code(v) = VOPND_MD;    VOPND_id(v) = m_vopnd_count++;    VMD_mdid(v) = mdid;    VMD_version(v) = version;    VMD_def(v) = NULL;    vec->set(version, v);    m_vopnd_vec.set(v->id(), v);    return v;}

//Register exact MD for each global variable.//Note you should call this function as early as possible, e.g, before process//all regions. Because that will assign smaller MD id to global variable.void RegionMgr::registerGlobalMD(){    //Only top region can do initialize MD for global variable.    ASSERT0(m_var_mgr);    VarVec * varvec = m_var_mgr->get_var_vec();    for (INT i = 0; i <= varvec->get_last_idx(); i++) {        VAR * v = varvec->get(i);        if (v == NULL || VAR_is_local(v)) {            continue;        }        ASSERT0(VAR_is_global(v));        //User sometime intentionally declare non-allocable        //global variable to custmized usage.        //ASSERT0(VAR_allocable(v));        if (v->is_string() && genDedicateStrMD() != NULL) {            continue;        }        //We allocate MDTab for VAR which is func-decl or fake as well.        //Since some Passes such as AA may need fake VAR to do analysis.        MD md;        MD_base(&md) = v;        MD_ofst(&md) = 0;        MD_size(&md) = v->getByteSize(get_type_mgr());        if (VAR_is_fake(v) || VAR_is_func_decl(v)) {            MD_ty(&md) = MD_UNBOUND;        } else {            MD_ty(&md) = MD_EXACT;        }        m_md_sys->registerMD(md);    }}

//Check that all basic blocks should only end with terminator IR.void IRBB::verify(){    UINT c = 0;    C<IR*> * ct;    for (IR * ir = BB_irlist(this).get_head(&ct);         ir != NULL; ir = BB_irlist(this).get_next(&ct)) {        ASSERT0(ir->is_single());        ASSERT0(ir->get_bb() == this);        switch (IR_code(ir)) {        case IR_ST:        case IR_STPR:        case IR_STARRAY:        case IR_IST:        case IR_PHI:        case IR_REGION:        case IR_CALL:        case IR_ICALL:        case IR_GOTO:        case IR_IGOTO:        case IR_TRUEBR:        case IR_FALSEBR:        case IR_RETURN:        case IR_SWITCH:            break;        default: ASSERT(0, ("BB does not supported this kind of IR."));        }        if (is_bb_down_boundary(ir)) {            ASSERT(ir == BB_last_ir(this), ("invalid BB down boundary."));        }        c++;    }    ASSERT0(c == getNumOfIR());}

//Before removing bb or change bb successor,//you need remove the related PHI operand if BB successor has PHI stmt.void IRBB::removeSuccessorDesignatePhiOpnd(CFG<IRBB, IR> * cfg, IRBB * succ){    ASSERT0(cfg && succ);    IR_CFG * ircfg = (IR_CFG*)cfg;    Region * ru = ircfg->get_ru();    UINT const pos = ircfg->WhichPred(this, succ);    for (IR * ir = BB_first_ir(succ); ir != NULL; ir = BB_next_ir(succ)) {        if (!ir->is_phi()) { break; }        ASSERT0(cnt_list(PHI_opnd_list(ir)) == succ->getNumOfPred(cfg));        IR * opnd;        UINT lpos = pos;        for (opnd = PHI_opnd_list(ir); lpos != 0; opnd = opnd->get_next()) {            ASSERT0(opnd);            lpos--;        }        if (opnd == NULL) {            //PHI does not contain any operand.            continue;        }        opnd->removeSSAUse();        ((CPhi*)ir)->removeOpnd(opnd);        ru->freeIRTree(opnd);    }}

//Copy dbx from 'src' to 'tgt'.void copyDbx(IR * tgt, IR const* src, Region * ru){    ASSERT0(ru);    if (IR_ai(src) == NULL) {        return;    }    DbxAttachInfo * src_da = (DbxAttachInfo*)IR_ai(src)->get(AI_DBX);    if (IR_ai(tgt) == NULL) {        if (src_da == NULL) {            return;        }        IR_ai(tgt) = ru->allocAIContainer();    }    ASSERT0(IR_ai(tgt));    if (src_da == NULL) {        IR_ai(tgt)->clean(AI_DBX);        return;    }    DbxAttachInfo * tgt_da = (DbxAttachInfo*)IR_ai(tgt)->get(AI_DBX);    if (tgt_da == NULL) {        tgt_da = (DbxAttachInfo*)smpoolMalloc(                     sizeof(DbxAttachInfo), ru->get_pool());        ASSERT0(tgt_da);        tgt_da->init();        IR_ai(tgt)->set((BaseAttachInfo*)tgt_da);    }    tgt_da->dbx.copy(src_da->dbx);}

void set_lineno(IR * ir, UINT lineno, Region * ru){    DbxAttachInfo * da;    ASSERT0(ru);    if (IR_ai(ir) == NULL) {        IR_ai(ir) = ru->allocAIContainer();        da = (DbxAttachInfo*)smpoolMalloc(                 sizeof(DbxAttachInfo), ru->get_pool());        ASSERT0(da);        da->init();        IR_ai(ir)->set((BaseAttachInfo*)da);    } else {        IR_ai(ir)->init();        da = (DbxAttachInfo*)IR_ai(ir)->get(AI_DBX);        if (da == NULL) {            da = (DbxAttachInfo*)smpoolMalloc(                     sizeof(DbxAttachInfo), ru->get_pool());            ASSERT0(da);            da->init();            ASSERT0(da);            IR_ai(ir)->set((BaseAttachInfo*)da);        }    }    DBX_lineno(&da->dbx) = lineno;}

//Before removing bb, revising phi opnd if there are phis//in one of bb's successors.void IRBB::removeSuccessorPhiOpnd(CFG<IRBB, IR> * cfg){    IR_CFG * ircfg = (IR_CFG*)cfg;    Region * ru = ircfg->get_ru();    Vertex * vex = ircfg->get_vertex(BB_id(this));    ASSERT0(vex);    for (EdgeC * out = VERTEX_out_list(vex);         out != NULL; out = EC_next(out)) {        Vertex * succ_vex = EDGE_to(EC_edge(out));        IRBB * succ = ircfg->get_bb(VERTEX_id(succ_vex));        ASSERT0(succ);        UINT const pos = ircfg->WhichPred(this, succ);        for (IR * ir = BB_first_ir(succ);             ir != NULL; ir = BB_next_ir(succ)) {            if (!ir->is_phi()) { break; }            ASSERT0(cnt_list(PHI_opnd_list(ir)) ==                     cnt_list(VERTEX_in_list(succ_vex)));            IR * opnd;            UINT lpos = pos;            for (opnd = PHI_opnd_list(ir);                 lpos != 0; opnd = IR_next(opnd)) {                ASSERT0(opnd);                lpos--;            }            opnd->removeSSAUse();            ((CPhi*)ir)->removeOpnd(opnd);            ru->freeIRTree(opnd);        }    }}

void CMarchingTet::_ExtractSurface(const int tm, CMarchingTetEdge *pSplitEdges, CVertexInfo *pVertInfo){	Vector4i tet;	Vector3f p0, p1, p2, p3, vert[4];	int i, v0, v1, v2, v3, vbuff[4];	const int nsplit = GetSplitVertexCount();	ASSERT0(nsplit>0);#ifdef _DEBUG	tet = m_tet;	int debn=163;	if (tet.x==debn || tet.y==debn|| tet.z==debn || tet.w==debn)		int asgag=1;	//if (nsplit!=2) return;#endif	//for the split vertices;	for (i=0; i<nsplit; i++){		if (i==0){			_getVerticesByExtractionSequence(0, pVertInfo, v0, v1, v2, v3);			tet = Vector4i(v0, v1, v2, v3);		}		else{			v0=tet.x, v1=tet.y, v2=tet.z, v3=tet.w;			const int vtmp = _getVerticeByExtractionSequence(i);	//get the second slit vertex			ChangeTetVertexSeq(vtmp, v0, v1, v2, v3);		}		_extractSurface4(tm, v0, v1, v2, v3, p0, p1, p2, p3, 0, pSplitEdges, pVertInfo);	}	if (nsplit==4) return;		//for the mesh vertices;	const int cc= GetNonSplitVertices(vbuff);	Vector3i tri(vbuff[0], vbuff[1], vbuff[2]), *pBaseTri=NULL;	switch(cc){	case 1:		pBaseTri = _lsearchDynamicVertex(vbuff[0], pVertInfo);		break;	case 2:		pBaseTri = _lsearchDynamicEdge(vbuff[0], vbuff[1], pVertInfo);		break;	case 3:		pBaseTri = &tri;		break;	}	ASSERT0(pBaseTri!=NULL);	_setupVertices(tet, pBaseTri, vbuff, cc, pVertInfo, vert);	for (i=0; i<cc; i++){		v0=tet.x, v1=tet.y, v2=tet.z, v3=tet.w;		ChangeTetVertexSeq(vbuff[i], v0, v1, v2, v3);		p0=_matchVertices(v0, tet, vert);		p1=_matchVertices(v1, tet, vert);		p2=_matchVertices(v2, tet, vert);		p3=_matchVertices(v3, tet, vert);		_extractSurface4(tm, v0, v1, v2, v3, p0, p1, p2, p3, 1, pSplitEdges, pVertInfo);	}}

PassMgr::PassMgr(Region * ru){    ASSERT0(ru);    m_pool = smpoolCreate(sizeof(TimeInfo) * 4, MEM_COMM);    m_ru = ru;    m_rumgr = ru->get_region_mgr();    m_tm = ru->get_type_mgr();    ASSERT0(m_tm);}

void CMarchingTet::_extractSurface3(const int tm, CMarchingTetEdge *pSplitEdges, CVertexInfo *pVertInfo){	int v0, v1, v2, v3, vtmp, eidx01, eidx02, eidx03;	Vector3f q0, p0, p1, p2, p3; 	//===========get the vertices and edges for 1st split===========	_getVerticesAndEdgesByExtractionSequence(0, pVertInfo, v0, v1, v2, v3, eidx01, eidx02, eidx03);	vtmp = _getVerticeByExtractionSequence(1);	//get the second slit vertex	reOrderVertices(vtmp, v1, v2, v3, eidx01, eidx02, eidx03); //v1=vtmp now	bool pflag = pVertInfo[v0].getParticleFlag();	if (pflag){		//find a base triangle , or not finding		int nmeshvert, meshvert[4];		nmeshvert= _getNoneParticleVertices(meshvert, pVertInfo);		if (nmeshvert==0){ //no vertex is still on a mesh, so no ref point;			p0 = pVertInfo[v0].m_vCurrPosition;			p1 = pVertInfo[v1].m_vCurrPosition;			p2 = pVertInfo[v2].m_vCurrPosition;			p3 = pVertInfo[v3].m_vCurrPosition;			_lockEdges(tm, v0, v1, v2, v3, pSplitEdges);			_lockEdges(tm, v1, v0, v2, v3, pSplitEdges);			_lockEdges(tm, v2, v0, v1, v3, pSplitEdges);			_lockEdges(tm, v3, v0, v1, v2, pSplitEdges);		}		else{			Vector3i* pBaseTri = _lsearchDynamicVertex(meshvert[0], pVertInfo);			ASSERT0(pBaseTri!=NULL);			p0 = _vertexChoice(v0, meshvert[0], *pBaseTri, pVertInfo);			p1 = _vertexChoice(v1, meshvert[0], *pBaseTri, pVertInfo);			p2 = _vertexChoice(v2, meshvert[0], *pBaseTri, pVertInfo);			p3 = _vertexChoice(v3, meshvert[0], *pBaseTri, pVertInfo);		}	}	else{		const Vector3i* pBaseTri=_lsearchDynamicVertex(v0, pVertInfo);		ASSERT0(pBaseTri!=NULL);		p0 = pVertInfo[v0].m_vCurrPosition;		p1 = _computeVirtualCoorForV0(v1, pBaseTri->x, pBaseTri->y, pBaseTri->z, pVertInfo);		p2 = _computeVirtualCoorForV0(v2, pBaseTri->x, pBaseTri->y, pBaseTri->z, pVertInfo);		p3 = _computeVirtualCoorForV0(v3, pBaseTri->x, pBaseTri->y, pBaseTri->z, pVertInfo);	}	_genPatchForFirstCut(tm, v0, v1, v2, v3, p0, p1, p2, p3, pSplitEdges, pVertInfo);	//===========get the vertices and edges for 2nd split============	vtmp=v0, v0=v1, v1=vtmp;		//swap v0, v1 to setup a sequence;	vtmp=v2, v2=v3, v3=vtmp;		//swap v2, v3;	q0 = p0; p0 = p1; p1 = q0;		//swap p0, p1	q0 = p2; p2 = p3; p3 = q0;		//swap p2, p3	_extractSurface2_1(tm, v0, v1, v2, v3, p0, p1, p2, p3, pSplitEdges, pVertInfo);	//===========get the vertices and edges for 3nd split============	_extractSurface2_1(tm, v2, v1, v3, v0, p2, p1, p3, p0, pSplitEdges, pVertInfo);	//===========get the vertices and edges for 4th split============	_extractSurface2_1(tm, v3, v1, v0, v2, p3, p1, p0, p2, pSplitEdges, pVertInfo);}

//Return true if 'occ' does not be modified till meeting 'use_ir'.//e.g://    xx = occ  //def_ir//    ..//    ..//    yy = xx  //use_ir////'def_ir': ir stmt.//'occ': opnd of 'def_ir'//'use_ir': stmt in use-list of 'def_ir'.bool IR_CP::is_available(IR const* def_ir, IR const* occ, IR * use_ir){    if (def_ir == use_ir) {    return false; }    if (occ->is_const()) { return true; }    //Need check overlapped MDSet.    //e.g: Suppose occ is '*p + *q', p->a, q->b.    //occ can NOT reach 'def_ir' if one of p, q, a, b    //modified during the path.    IRBB * defbb = def_ir->get_bb();    IRBB * usebb = use_ir->get_bb();    if (defbb == usebb) {        //Both def_ir and use_ir are in same BB.        C<IR*> * ir_holder = NULL;        bool f = BB_irlist(defbb).find(const_cast<IR*>(def_ir), &ir_holder);        CK_USE(f);        IR * ir;        for (ir = BB_irlist(defbb).get_next(&ir_holder);             ir != NULL && ir != use_ir;             ir = BB_irlist(defbb).get_next(&ir_holder)) {            if (m_du->is_may_def(ir, occ, true)) {                return false;            }        }        if (ir == NULL) {            ;//use_ir appears prior to def_ir. Do more check via live_in_expr.        } else {            ASSERT(ir == use_ir, ("def_ir should be in same bb to use_ir"));            return true;        }    }    ASSERT0(use_ir->is_stmt());    DefDBitSetCore const* availin_expr =        m_du->getAvailInExpr(BB_id(usebb), NULL);    ASSERT0(availin_expr);    if (availin_expr->is_contain(IR_id(occ))) {        IR * u;        for (u = BB_first_ir(usebb); u != use_ir && u != NULL;             u = BB_next_ir(usebb)) {            //Check if 'u' override occ's value.            if (m_du->is_may_def(u, occ, true)) {                return false;            }        }        ASSERT(u != NULL && u == use_ir,                ("Not find use_ir in bb, may be it has "                 "been removed by other optimization"));        return true;    }    return false;}

/*Perform general optimizaitions.Basis step to do:    1. Build control flow.    2. Compute data flow dependence.    3. Compute live expression info.Optimizations to be performed:    1. GCSE    2. DCE    3. RVI(register variable recog)    4. IVR(induction variable elimination)    5. CP(constant propagation)    6. CP(copy propagation)    7. SCCP (Sparse Conditional Constant Propagation).    8. PRE (Partial Redundancy Elimination) with strength reduction.    9. Dominator-based optimizations such as copy propagation,        constant propagation and redundancy elimination using        value numbering.    10. Must-alias analysis, to convert pointer de-references        into regular variable references whenever possible.    11. Scalar Replacement of Aggregates, to convert structure        references into scalar references that can be optimized        using the standard scalar passes.*/bool Region::MiddleProcess(OptCtx & oc){    if (g_opt_level != NO_OPT) {        PassMgr * passmgr = get_pass_mgr();        ASSERT0(passmgr);        //Perform scalar optimizations.        passmgr->performScalarOpt(oc);    }    ASSERT0(verifyRPO(oc));    BBList * bbl = get_bb_list();    if (bbl->get_elem_count() == 0) { return true; }    SimpCtx simp;    simp.set_simp_cf();    simp.set_simp_array();    simp.set_simp_select();    simp.set_simp_land_lor();    simp.set_simp_lnot();    simp.set_simp_ild_ist();    simp.set_simp_to_lowest_height();    simplifyBBlist(bbl, &simp);    if (g_cst_bb_list && SIMP_need_recon_bblist(&simp)) {        if (reconstructBBlist(oc) && g_do_cfg) {            //Before CFG building.            get_cfg()->removeEmptyBB(oc);            get_cfg()->rebuild(oc);            //After CFG building, it is perform different            //operation to before building.            get_cfg()->removeEmptyBB(oc);            get_cfg()->computeExitList();            if (g_do_cdg) {                ASSERT0(get_pass_mgr());                CDG * cdg = (CDG*)get_pass_mgr()->registerPass(PASS_CDG);                cdg->rebuild(oc, *get_cfg());            }        }    }    ASSERT0(verifyIRandBB(bbl, this));    if (g_do_refine) {        RefineCtx rf;        refineBBlist(bbl, rf);        ASSERT0(verifyIRandBB(bbl, this));    }    return true;}

voidrange_tree_swap(range_tree_t **rtsrc, range_tree_t **rtdst){	range_tree_t *rt;	ASSERT0(range_tree_space(*rtdst));	ASSERT0(avl_numnodes(&(*rtdst)->rt_root));	rt = *rtsrc;	*rtsrc = *rtdst;	*rtdst = rt;}

kthread_t *zk_thread_create(caddr_t stk, size_t stksize, thread_func_t func, void *arg,    uint64_t len, proc_t *pp, int state, pri_t pri, int detachstate){	kthread_t *kt;	pthread_attr_t attr;	char *stkstr;	ASSERT0(state & ~TS_RUN);	ASSERT0(len);	kt = umem_zalloc(sizeof (kthread_t), UMEM_NOFAIL);	kt->t_func = func;	kt->t_arg = arg;	kt->t_pri = pri;	VERIFY0(pthread_attr_init(&attr));	VERIFY0(pthread_attr_setdetachstate(&attr, detachstate));	/*	 * We allow the default stack size in user space to be specified by	 * setting the ZFS_STACK_SIZE environment variable.  This allows us	 * the convenience of observing and debugging stack overruns in	 * user space.  Explicitly specified stack sizes will be honored.	 * The usage of ZFS_STACK_SIZE is discussed further in the	 * ENVIRONMENT VARIABLES sections of the ztest(1) man page.	 */	if (stksize == 0) {		stkstr = getenv("ZFS_STACK_SIZE");		if (stkstr == NULL)			stksize = TS_STACK_MAX;		else			stksize = MAX(atoi(stkstr), TS_STACK_MIN);	}	VERIFY3S(stksize, >, 0);	stksize = P2ROUNDUP(MAX(stksize, TS_STACK_MIN), PAGESIZE);	/*	 * If this ever fails, it may be because the stack size is not a	 * multiple of system page size.	 */	VERIFY0(pthread_attr_setstacksize(&attr, stksize));	VERIFY0(pthread_attr_setguardsize(&attr, PAGESIZE));	VERIFY0(pthread_create(&kt->t_tid, &attr, &zk_thread_helper, kt));	VERIFY0(pthread_attr_destroy(&attr));	return (kt);}

ExpRep * IR_EXPR_TAB::encode_expr(IN IR * ir){    if (ir == NULL) return NULL;    ASSERT0(ir->is_exp());    switch (IR_code(ir)) {    case IR_ID:    case IR_LD:    case IR_LDA:    case IR_CONST:    case IR_PR:        return NULL;    case IR_ILD:    case IR_ADD:    case IR_SUB:    case IR_MUL:    case IR_DIV:    case IR_REM:    case IR_MOD:    case IR_LAND: //logical and &&    case IR_LOR: //logical or ||    case IR_BAND: //bit and &    case IR_BOR: //bit or |    case IR_XOR:    case IR_BNOT: //bitwise not    case IR_LNOT: //logical not    case IR_NEG:    case IR_LT:    case IR_LE:    case IR_GT:    case IR_GE:    case IR_EQ:    case IR_NE:    case IR_ARRAY:    case IR_ASR:    case IR_LSR:    case IR_LSL:    case IR_CVT: //type convertion    case IR_SELECT: //formulized determinate-expr?exp:exp        {            ExpRep * ie = append_expr(ir);            ASSERT(!EXPR_occ_list(ie).find(ir),                    ("process same IR repeated."));            EXPR_occ_list(ie).append_tail(ir);            return ie;        }    default: ASSERT0(0);    }    return NULL;}