自学教程：C++ DRM_ERROR函数代码示例

/* * Init DSI DPI encoder. * Allocate an mdfld_dsi_encoder and attach it to given @dsi_connector * return pointer of newly allocated DPI encoder, NULL on error */struct mdfld_dsi_encoder *mdfld_dsi_dpi_init(struct drm_device *dev,				struct mdfld_dsi_connector *dsi_connector,				const struct panel_funcs *p_funcs){	struct mdfld_dsi_dpi_output *dpi_output = NULL;	struct mdfld_dsi_config *dsi_config;	struct drm_connector *connector = NULL;	struct drm_encoder *encoder = NULL;	int pipe;	u32 data;	int ret;	pipe = dsi_connector->pipe;	if (mdfld_get_panel_type(dev, pipe) != TC35876X) {		dsi_config = mdfld_dsi_get_config(dsi_connector);		/* panel hard-reset */		if (p_funcs->reset) {			ret = p_funcs->reset(pipe);			if (ret) {				DRM_ERROR("Panel %d hard-reset failed/n", pipe);				return NULL;			}		}		/* panel drvIC init */		if (p_funcs->drv_ic_init)			p_funcs->drv_ic_init(dsi_config, pipe);		/* panel power mode detect */		ret = mdfld_dsi_get_power_mode(dsi_config, &data, false);		if (ret) {			DRM_ERROR("Panel %d get power mode failed/n", pipe);			dsi_connector->status = connector_status_disconnected;		} else {			DRM_INFO("pipe %d power mode 0x%x/n", pipe, data);			dsi_connector->status = connector_status_connected;		}	}	dpi_output = kzalloc(sizeof(struct mdfld_dsi_dpi_output), GFP_KERNEL);	if (!dpi_output) {		DRM_ERROR("No memory/n");		return NULL;	}	dpi_output->panel_on = 0;	dpi_output->dev = dev;	if (mdfld_get_panel_type(dev, pipe) != TC35876X)		dpi_output->p_funcs = p_funcs;	dpi_output->first_boot = 1;	/*get fixed mode*/	dsi_config = mdfld_dsi_get_config(dsi_connector);	/*create drm encoder object*/	connector = &dsi_connector->base.base;	encoder = &dpi_output->base.base.base;	drm_encoder_init(dev,			encoder,			p_funcs->encoder_funcs,			DRM_MODE_ENCODER_LVDS, NULL);	drm_encoder_helper_add(encoder,				p_funcs->encoder_helper_funcs);	/*attach to given connector*/	drm_connector_attach_encoder(connector, encoder);	/*set possible crtcs and clones*/	if (dsi_connector->pipe) {		encoder->possible_crtcs = (1 << 2);		encoder->possible_clones = (1 << 1);	} else {		encoder->possible_crtcs = (1 << 0);		encoder->possible_clones = (1 << 0);	}	dsi_connector->base.encoder = &dpi_output->base.base;	return &dpi_output->base;}

void mdfld_panel_generic_dsi_dbi_update_fb(	struct mdfld_dsi_dbi_output *dbi_output,	int pipe){	struct mdfld_dsi_pkg_sender *sender =		mdfld_dsi_encoder_get_pkg_sender(&dbi_output->base);	struct drm_device *dev = dbi_output->dev;	struct drm_psb_private *dev_priv = dev->dev_private;	struct drm_crtc *crtc = dbi_output->base.base.crtc;	struct psb_intel_crtc *psb_crtc =		(crtc) ? to_psb_intel_crtc(crtc) : NULL;	u32 dpll_reg = MRST_DPLL_A;	u32 dspcntr_reg = DSPACNTR;	u32 pipeconf_reg = PIPEACONF;	u32 dsplinoff_reg = DSPALINOFF;	u32 dspsurf_reg = DSPASURF;	if (!dev_priv->dsi_init_done)		return;	/* if mode setting on-going, back off */	if ((dbi_output->mode_flags & MODE_SETTING_ON_GOING) ||			(psb_crtc &&			 (psb_crtc->mode_flags & MODE_SETTING_ON_GOING)) ||			!(dbi_output->mode_flags & MODE_SETTING_ENCODER_DONE))		return;	if (pipe == 2) {		dspcntr_reg = DSPCCNTR;		pipeconf_reg = PIPECCONF;		dsplinoff_reg = DSPCLINOFF;		dspsurf_reg = DSPCSURF;	}	if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,				OSPM_UHB_FORCE_POWER_ON)) {		DRM_ERROR("hw begin failed/n");		return;	}	/* check DBI FIFO status */	if (!(REG_READ(dpll_reg) & DPLL_VCO_ENABLE) ||	   !(REG_READ(dspcntr_reg) & DISPLAY_PLANE_ENABLE) ||	   !(REG_READ(pipeconf_reg) & DISPLAY_PLANE_ENABLE)) {		goto update_fb_out0;	}	/* refresh plane changes */	REG_WRITE(dsplinoff_reg, REG_READ(dsplinoff_reg));	REG_WRITE(dspsurf_reg, REG_READ(dspsurf_reg));	REG_READ(dspsurf_reg);	mdfld_dsi_send_dcs(sender,			   write_mem_start,			   NULL,			   0,			   CMD_DATA_SRC_PIPE,			   MDFLD_DSI_SEND_PACKAGE);	dbi_output->dsr_fb_update_done = true;update_fb_out0:	ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);}

static int armada_fb_create(struct drm_fb_helper *fbh,	struct drm_fb_helper_surface_size *sizes){	struct drm_device *dev = fbh->dev;	struct drm_mode_fb_cmd2 mode;	struct armada_framebuffer *dfb;	struct armada_gem_object *obj;	struct fb_info *info;	int size, ret;	void *ptr;	memset(&mode, 0, sizeof(mode));	mode.width = sizes->surface_width;	mode.height = sizes->surface_height;	mode.pitches[0] = armada_pitch(mode.width, sizes->surface_bpp);	mode.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,					sizes->surface_depth);	size = mode.pitches[0] * mode.height;	obj = armada_gem_alloc_private_object(dev, size);	if (!obj) {		DRM_ERROR("failed to allocate fb memory/n");		return -ENOMEM;	}	ret = armada_gem_linear_back(dev, obj);	if (ret) {		drm_gem_object_unreference_unlocked(&obj->obj);		return ret;	}	ptr = armada_gem_map_object(dev, obj);	if (!ptr) {		drm_gem_object_unreference_unlocked(&obj->obj);		return -ENOMEM;	}	dfb = armada_framebuffer_create(dev, &mode, obj);	/*	 * A reference is now held by the framebuffer object if	 * successful, otherwise this drops the ref for the error path.	 */	drm_gem_object_unreference_unlocked(&obj->obj);	if (IS_ERR(dfb))		return PTR_ERR(dfb);	info = drm_fb_helper_alloc_fbi(fbh);	if (IS_ERR(info)) {		ret = PTR_ERR(info);		goto err_fballoc;	}	strlcpy(info->fix.id, "armada-drmfb", sizeof(info->fix.id));	info->par = fbh;	info->flags = FBINFO_DEFAULT | FBINFO_CAN_FORCE_OUTPUT;	info->fbops = &armada_fb_ops;	info->fix.smem_start = obj->phys_addr;	info->fix.smem_len = obj->obj.size;	info->screen_size = obj->obj.size;	info->screen_base = ptr;	fbh->fb = &dfb->fb;	drm_fb_helper_fill_fix(info, dfb->fb.pitches[0], dfb->fb.depth);	drm_fb_helper_fill_var(info, fbh, sizes->fb_width, sizes->fb_height);	DRM_DEBUG_KMS("allocated %dx%d %dbpp fb: 0x%08llx/n",		dfb->fb.width, dfb->fb.height, dfb->fb.bits_per_pixel,		(unsigned long long)obj->phys_addr);	return 0; err_fballoc:	dfb->fb.funcs->destroy(&dfb->fb);	return ret;}

static int render_state_setup(struct render_state *so){	struct drm_device *dev = so->vma->vm->dev;	const struct intel_renderstate_rodata *rodata = so->rodata;	const bool has_64bit_reloc = INTEL_GEN(dev) >= 8;	unsigned int i = 0, reloc_index = 0;	struct page *page;	u32 *d;	int ret;	ret = i915_gem_object_set_to_cpu_domain(so->vma->obj, true);	if (ret)		return ret;	page = i915_gem_object_get_dirty_page(so->vma->obj, 0);	d = kmap(page);	while (i < rodata->batch_items) {		u32 s = rodata->batch[i];		if (i * 4  == rodata->reloc[reloc_index]) {			u64 r = s + so->vma->node.start;			s = lower_32_bits(r);			if (has_64bit_reloc) {				if (i + 1 >= rodata->batch_items ||				    rodata->batch[i + 1] != 0) {					ret = -EINVAL;					goto err_out;				}				d[i++] = s;				s = upper_32_bits(r);			}			reloc_index++;		}		d[i++] = s;	}	while (i % CACHELINE_DWORDS)		OUT_BATCH(d, i, MI_NOOP);	so->aux_batch_offset = i * sizeof(u32);	if (HAS_POOLED_EU(dev)) {		/*		 * We always program 3x6 pool config but depending upon which		 * subslice is disabled HW drops down to appropriate config		 * shown below.		 *		 * In the below table 2x6 config always refers to		 * fused-down version, native 2x6 is not available and can		 * be ignored		 *		 * SNo  subslices config                eu pool configuration		 * -----------------------------------------------------------		 * 1    3 subslices enabled (3x6)  -    0x00777000  (9+9)		 * 2    ss0 disabled (2x6)         -    0x00777000  (3+9)		 * 3    ss1 disabled (2x6)         -    0x00770000  (6+6)		 * 4    ss2 disabled (2x6)         -    0x00007000  (9+3)		 */		u32 eu_pool_config = 0x00777000;		OUT_BATCH(d, i, GEN9_MEDIA_POOL_STATE);		OUT_BATCH(d, i, GEN9_MEDIA_POOL_ENABLE);		OUT_BATCH(d, i, eu_pool_config);		OUT_BATCH(d, i, 0);		OUT_BATCH(d, i, 0);		OUT_BATCH(d, i, 0);	}	OUT_BATCH(d, i, MI_BATCH_BUFFER_END);	so->aux_batch_size = (i * sizeof(u32)) - so->aux_batch_offset;	/*	 * Since we are sending length, we need to strictly conform to	 * all requirements. For Gen2 this must be a multiple of 8.	 */	so->aux_batch_size = ALIGN(so->aux_batch_size, 8);	kunmap(page);	ret = i915_gem_object_set_to_gtt_domain(so->vma->obj, false);	if (ret)		return ret;	if (rodata->reloc[reloc_index] != -1) {		DRM_ERROR("only %d relocs resolved/n", reloc_index);		return -EINVAL;	}	return 0;err_out:	kunmap(page);	return ret;}

static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info){	bool clock_recovery; 	u8 voltage;	int i;	radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);	memset(dp_info->train_set, 0, 4);	radeon_dp_update_vs_emph(dp_info);	udelay(400);	/* clock recovery loop */	clock_recovery = false;	dp_info->tries = 0;	voltage = 0xff;	while (1) {		drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);		if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) {			DRM_ERROR("displayport link status failed/n");			break;		}		if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {			clock_recovery = true;			break;		}		for (i = 0; i < dp_info->dp_lane_count; i++) {			if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)				break;		}		if (i == dp_info->dp_lane_count) {			DRM_ERROR("clock recovery reached max voltage/n");			break;		}		if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {			++dp_info->tries;			if (dp_info->tries == 5) {				DRM_ERROR("clock recovery tried 5 times/n");				break;			}		} else			dp_info->tries = 0;		voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;		/* Compute new train_set as requested by sink */		dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);		radeon_dp_update_vs_emph(dp_info);	}	if (!clock_recovery) {		DRM_ERROR("clock recovery failed/n");		return -1;	} else {		DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d/n",			  dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,			  (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>			  DP_TRAIN_PRE_EMPHASIS_SHIFT);		return 0;	}}

static int init_ring_common(struct intel_ring_buffer *ring){    drm_i915_private_t *dev_priv = ring->dev->dev_private;    struct drm_i915_gem_object *obj = ring->obj;    u32 head;    /* Stop the ring if it's running. */    I915_WRITE_CTL(ring, 0);    I915_WRITE_HEAD(ring, 0);    ring->write_tail(ring, 0);    /* Initialize the ring. */    I915_WRITE_START(ring, obj->gtt_offset);    head = I915_READ_HEAD(ring) & HEAD_ADDR;    /* G45 ring initialization fails to reset head to zero */    if (head != 0) {        DRM_DEBUG_KMS("%s head not reset to zero "                      "ctl %08x head %08x tail %08x start %08x/n",                      ring->name,                      I915_READ_CTL(ring),                      I915_READ_HEAD(ring),                      I915_READ_TAIL(ring),                      I915_READ_START(ring));        I915_WRITE_HEAD(ring, 0);        if (I915_READ_HEAD(ring) & HEAD_ADDR) {            DRM_ERROR("failed to set %s head to zero "                      "ctl %08x head %08x tail %08x start %08x/n",                      ring->name,                      I915_READ_CTL(ring),                      I915_READ_HEAD(ring),                      I915_READ_TAIL(ring),                      I915_READ_START(ring));        }    }    I915_WRITE_CTL(ring,                   ((ring->size - PAGE_SIZE) & RING_NR_PAGES)                   | RING_REPORT_64K | RING_VALID);    /* If the head is still not zero, the ring is dead */    if ((I915_READ_CTL(ring) & RING_VALID) == 0 ||            I915_READ_START(ring) != obj->gtt_offset ||            (I915_READ_HEAD(ring) & HEAD_ADDR) != 0) {        DRM_ERROR("%s initialization failed "                  "ctl %08x head %08x tail %08x start %08x/n",                  ring->name,                  I915_READ_CTL(ring),                  I915_READ_HEAD(ring),                  I915_READ_TAIL(ring),                  I915_READ_START(ring));        return -EIO;    }    if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))        i915_kernel_lost_context(ring->dev);    else {        ring->head = I915_READ_HEAD(ring);        ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;        ring->space = ring_space(ring);    }    return 0;}

int drm_update_drawable_info(struct drm_device *dev, void *data, struct drm_file *file_priv){    struct drm_update_draw *update = data;    unsigned long irqflags;    struct drm_clip_rect *rects;    struct drm_drawable_info *info;    int err;    info = idr_find(&dev->drw_idr, update->handle);    if (!info) {        info = drm_calloc(1, sizeof(*info), DRM_MEM_BUFS);        if (!info)            return -ENOMEM;        if (IS_ERR(idr_replace(&dev->drw_idr, info, update->handle))) {            DRM_ERROR("No such drawable %d/n", update->handle);            drm_free(info, sizeof(*info), DRM_MEM_BUFS);            return -EINVAL;        }    }    switch (update->type) {    case DRM_DRAWABLE_CLIPRECTS:        if (update->num != info->num_rects) {            rects = drm_alloc(update->num * sizeof(struct drm_clip_rect),                     DRM_MEM_BUFS);        } else            rects = info->rects;        if (update->num && !rects) {            DRM_ERROR("Failed to allocate cliprect memory/n");            err = -ENOMEM;            goto error;        }        if (update->num && DRM_COPY_FROM_USER(rects,                             (struct drm_clip_rect __user *)                             (unsigned long)update->data,                             update->num *                             sizeof(*rects))) {            DRM_ERROR("Failed to copy cliprects from userspace/n");            err = -EFAULT;            goto error;        }        spin_lock_irqsave(&dev->drw_lock, irqflags);        if (rects != info->rects) {            drm_free(info->rects, info->num_rects *                 sizeof(struct drm_clip_rect), DRM_MEM_BUFS);        }        info->rects = rects;        info->num_rects = update->num;        spin_unlock_irqrestore(&dev->drw_lock, irqflags);        DRM_DEBUG("Updated %d cliprects for drawable %d/n",              info->num_rects, update->handle);        break;    default:        DRM_ERROR("Invalid update type %d/n", update->type);        return -EINVAL;    }    return 0;error:    if (rects != info->rects)        drm_free(rects, update->num * sizeof(struct drm_clip_rect),             DRM_MEM_BUFS);    return err;}

int vmw_du_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,			   uint32_t handle, uint32_t width, uint32_t height){	struct vmw_private *dev_priv = vmw_priv(crtc->dev);	struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;	struct vmw_display_unit *du = vmw_crtc_to_du(crtc);	struct vmw_surface *surface = NULL;	struct vmw_dma_buffer *dmabuf = NULL;	int ret;	if (handle) {		ret = vmw_user_surface_lookup_handle(dev_priv, tfile,						     handle, &surface);		if (!ret) {			if (!surface->snooper.image) {				DRM_ERROR("surface not suitable for cursor/n");				return -EINVAL;			}		} else {			ret = vmw_user_dmabuf_lookup(tfile,						     handle, &dmabuf);			if (ret) {				DRM_ERROR("failed to find surface or dmabuf: %i/n", ret);				return -EINVAL;			}		}	}	/* takedown old cursor */	if (du->cursor_surface) {		du->cursor_surface->snooper.crtc = NULL;		vmw_surface_unreference(&du->cursor_surface);	}	if (du->cursor_dmabuf)		vmw_dmabuf_unreference(&du->cursor_dmabuf);	/* setup new image */	if (surface) {		/* vmw_user_surface_lookup takes one reference */		du->cursor_surface = surface;		du->cursor_surface->snooper.crtc = crtc;		du->cursor_age = du->cursor_surface->snooper.age;		vmw_cursor_update_image(dev_priv, surface->snooper.image,					64, 64, du->hotspot_x, du->hotspot_y);	} else if (dmabuf) {		struct ttm_bo_kmap_obj map;		unsigned long kmap_offset;		unsigned long kmap_num;		void *virtual;		bool dummy;		/* vmw_user_surface_lookup takes one reference */		du->cursor_dmabuf = dmabuf;		kmap_offset = 0;		kmap_num = (64*64*4) >> PAGE_SHIFT;		ret = ttm_bo_reserve(&dmabuf->base, true, false, false, 0);		if (unlikely(ret != 0)) {			DRM_ERROR("reserve failed/n");			return -EINVAL;		}		ret = ttm_bo_kmap(&dmabuf->base, kmap_offset, kmap_num, &map);		if (unlikely(ret != 0))			goto err_unreserve;		virtual = ttm_kmap_obj_virtual(&map, &dummy);		vmw_cursor_update_image(dev_priv, virtual, 64, 64,					du->hotspot_x, du->hotspot_y);		ttm_bo_kunmap(&map);err_unreserve:		ttm_bo_unreserve(&dmabuf->base);	} else {

/* dm_helpers_parse_edid_caps * * Parse edid caps * * @edid:	[in] pointer to edid *  edid_caps:	[in] pointer to edid caps * @return *	void * */enum dc_edid_status dm_helpers_parse_edid_caps(		struct dc_context *ctx,		const struct dc_edid *edid,		struct dc_edid_caps *edid_caps){	struct edid *edid_buf = (struct edid *) edid->raw_edid;	struct cea_sad *sads;	int sad_count = -1;	int sadb_count = -1;	int i = 0;	int j = 0;	uint8_t *sadb = NULL;	enum dc_edid_status result = EDID_OK;	if (!edid_caps || !edid)		return EDID_BAD_INPUT;	if (!drm_edid_is_valid(edid_buf))		result = EDID_BAD_CHECKSUM;	edid_caps->manufacturer_id = (uint16_t) edid_buf->mfg_id[0] |					((uint16_t) edid_buf->mfg_id[1])<<8;	edid_caps->product_id = (uint16_t) edid_buf->prod_code[0] |					((uint16_t) edid_buf->prod_code[1])<<8;	edid_caps->serial_number = edid_buf->serial;	edid_caps->manufacture_week = edid_buf->mfg_week;	edid_caps->manufacture_year = edid_buf->mfg_year;	/* One of the four detailed_timings stores the monitor name. It's	 * stored in an array of length 13. */	for (i = 0; i < 4; i++) {		if (edid_buf->detailed_timings[i].data.other_data.type == 0xfc) {			while (j < 13 && edid_buf->detailed_timings[i].data.other_data.data.str.str[j]) {				if (edid_buf->detailed_timings[i].data.other_data.data.str.str[j] == '/n')					break;				edid_caps->display_name[j] =					edid_buf->detailed_timings[i].data.other_data.data.str.str[j];				j++;			}		}	}	edid_caps->edid_hdmi = drm_detect_hdmi_monitor(			(struct edid *) edid->raw_edid);	sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads);	if (sad_count <= 0) {		DRM_INFO("SADs count is: %d, don't need to read it/n",				sad_count);		return result;	}	edid_caps->audio_mode_count = sad_count < DC_MAX_AUDIO_DESC_COUNT ? sad_count : DC_MAX_AUDIO_DESC_COUNT;	for (i = 0; i < edid_caps->audio_mode_count; ++i) {		struct cea_sad *sad = &sads[i];		edid_caps->audio_modes[i].format_code = sad->format;		edid_caps->audio_modes[i].channel_count = sad->channels + 1;		edid_caps->audio_modes[i].sample_rate = sad->freq;		edid_caps->audio_modes[i].sample_size = sad->byte2;	}	sadb_count = drm_edid_to_speaker_allocation((struct edid *) edid->raw_edid, &sadb);	if (sadb_count < 0) {		DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d/n", sadb_count);		sadb_count = 0;	}	if (sadb_count)		edid_caps->speaker_flags = sadb[0];	else		edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION;	kfree(sads);	kfree(sadb);	return result;}

/** * i965_reset - reset chip after a hang * @dev: drm device to reset * @flags: reset domains * * Reset the chip.  Useful if a hang is detected. Returns zero on successful * reset or otherwise an error code. * * Procedure is fairly simple: *   - reset the chip using the reset reg *   - re-init context state *   - re-init hardware status page *   - re-init ring buffer *   - re-init interrupt state *   - re-init display */int i915_reset(struct drm_device *dev, u8 flags){	drm_i915_private_t *dev_priv = dev->dev_private;	/*	 * We really should only reset the display subsystem if we actually	 * need to	 */	bool need_display = true;	int ret;	if (!i915_try_reset)		return 0;	if (!mutex_trylock(&dev->struct_mutex))		return -EBUSY;	i915_gem_reset(dev);	ret = -ENODEV;	if (get_seconds() - dev_priv->last_gpu_reset < 5) {		DRM_ERROR("GPU hanging too fast, declaring wedged!/n");	} else switch (INTEL_INFO(dev)->gen) {	case 7:	case 6:		ret = gen6_do_reset(dev, flags);		break;	case 5:		ret = ironlake_do_reset(dev, flags);		break;	case 4:		ret = i965_do_reset(dev, flags);		break;	case 2:		ret = i8xx_do_reset(dev, flags);		break;	}	dev_priv->last_gpu_reset = get_seconds();	if (ret) {		DRM_ERROR("Failed to reset chip./n");		mutex_unlock(&dev->struct_mutex);		return ret;	}	/* Ok, now get things going again... */	/*	 * Everything depends on having the GTT running, so we need to start	 * there.  Fortunately we don't need to do this unless we reset the	 * chip at a PCI level.	 *	 * Next we need to restore the context, but we don't use those	 * yet either...	 *	 * Ring buffer needs to be re-initialized in the KMS case, or if X	 * was running at the time of the reset (i.e. we weren't VT	 * switched away).	 */	if (drm_core_check_feature(dev, DRIVER_MODESET) ||			!dev_priv->mm.suspended) {		dev_priv->mm.suspended = 0;		dev_priv->ring[RCS].init(&dev_priv->ring[RCS]);		if (HAS_BSD(dev))		    dev_priv->ring[VCS].init(&dev_priv->ring[VCS]);		if (HAS_BLT(dev))		    dev_priv->ring[BCS].init(&dev_priv->ring[BCS]);		mutex_unlock(&dev->struct_mutex);		drm_irq_uninstall(dev);		drm_mode_config_reset(dev);		drm_irq_install(dev);		mutex_lock(&dev->struct_mutex);	}	mutex_unlock(&dev->struct_mutex);	/*	 * Perform a full modeset as on later generations, e.g. Ironlake, we may	 * need to retrain the display link and cannot just restore the register	 * values.	 */	if (need_display) {		mutex_lock(&dev->mode_config.mutex);		drm_helper_resume_force_mode(dev);//.........这里部分代码省略.........

static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,			      const struct firmware *fw){	struct intel_css_header *css_header;	struct intel_package_header *package_header;	struct intel_dmc_header *dmc_header;	struct intel_csr *csr = &dev_priv->csr;	const struct stepping_info *si = intel_get_stepping_info(dev_priv);	uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;	uint32_t i;	uint32_t *dmc_payload;	uint32_t required_version;	if (!fw)		return NULL;	/* Extract CSS Header information*/	css_header = (struct intel_css_header *)fw->data;	if (sizeof(struct intel_css_header) !=	    (css_header->header_len * 4)) {		DRM_ERROR("Firmware has wrong CSS header length %u bytes/n",			  (css_header->header_len * 4));		return NULL;	}	csr->version = css_header->version;	if (IS_GEMINILAKE(dev_priv)) {		required_version = GLK_CSR_VERSION_REQUIRED;	} else if (IS_KABYLAKE(dev_priv)) {		required_version = KBL_CSR_VERSION_REQUIRED;	} else if (IS_SKYLAKE(dev_priv)) {		required_version = SKL_CSR_VERSION_REQUIRED;	} else if (IS_BROXTON(dev_priv)) {		required_version = BXT_CSR_VERSION_REQUIRED;	} else {		MISSING_CASE(INTEL_REVID(dev_priv));		required_version = 0;	}	if (csr->version != required_version) {		DRM_INFO("Refusing to load DMC firmware v%u.%u,"			 " please use v%u.%u [" FIRMWARE_URL "]./n",			 CSR_VERSION_MAJOR(csr->version),			 CSR_VERSION_MINOR(csr->version),			 CSR_VERSION_MAJOR(required_version),			 CSR_VERSION_MINOR(required_version));		return NULL;	}	readcount += sizeof(struct intel_css_header);	/* Extract Package Header information*/	package_header = (struct intel_package_header *)		&fw->data[readcount];	if (sizeof(struct intel_package_header) !=	    (package_header->header_len * 4)) {		DRM_ERROR("Firmware has wrong package header length %u bytes/n",			  (package_header->header_len * 4));		return NULL;	}	readcount += sizeof(struct intel_package_header);	/* Search for dmc_offset to find firware binary. */	for (i = 0; i < package_header->num_entries; i++) {		if (package_header->fw_info[i].substepping == '*' &&		    si->stepping == package_header->fw_info[i].stepping) {			dmc_offset = package_header->fw_info[i].offset;			break;		} else if (si->stepping == package_header->fw_info[i].stepping &&			   si->substepping == package_header->fw_info[i].substepping) {			dmc_offset = package_header->fw_info[i].offset;			break;		} else if (package_header->fw_info[i].stepping == '*' &&			   package_header->fw_info[i].substepping == '*')			dmc_offset = package_header->fw_info[i].offset;	}	if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {		DRM_ERROR("Firmware not supported for %c stepping/n",			  si->stepping);		return NULL;	}	readcount += dmc_offset;	/* Extract dmc_header information. */	dmc_header = (struct intel_dmc_header *)&fw->data[readcount];	if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) {		DRM_ERROR("Firmware has wrong dmc header length %u bytes/n",			  (dmc_header->header_len));		return NULL;	}	readcount += sizeof(struct intel_dmc_header);	/* Cache the dmc header info. */	if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {		DRM_ERROR("Firmware has wrong mmio count %u/n",			  dmc_header->mmio_count);		return NULL;	}	csr->mmio_count = dmc_header->mmio_count;//.........这里部分代码省略.........

static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v){    DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X/n",              reg, v);    BUG_ON(1);}

/* * Registers accessors functions. */static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg){    DRM_ERROR("Invalid callback to read register 0x%04X/n", reg);    BUG_ON(1);    return 0;}

/** * Detects bit 6 swizzling of address lookup between IGD access and CPU * access through main memory. */voidi915_gem_detect_bit_6_swizzle(struct drm_device *dev){	drm_i915_private_t *dev_priv = dev->dev_private;	uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;	uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;	if (INTEL_INFO(dev)->gen >= 5) {		/* On Ironlake whatever DRAM config, GPU always do		 * same swizzling setup.		 */		swizzle_x = I915_BIT_6_SWIZZLE_9_10;		swizzle_y = I915_BIT_6_SWIZZLE_9;	} else if (IS_GEN2(dev)) {		/* As far as we know, the 865 doesn't have these bit 6		 * swizzling issues.		 */		swizzle_x = I915_BIT_6_SWIZZLE_NONE;		swizzle_y = I915_BIT_6_SWIZZLE_NONE;	} else if (IS_MOBILE(dev)) {		uint32_t dcc;		/* On mobile 9xx chipsets, channel interleave by the CPU is		 * determined by DCC.  For single-channel, neither the CPU		 * nor the GPU do swizzling.  For dual channel interleaved,		 * the GPU's interleave is bit 9 and 10 for X tiled, and bit		 * 9 for Y tiled.  The CPU's interleave is independent, and		 * can be based on either bit 11 (haven't seen this yet) or		 * bit 17 (common).		 */		dcc = I915_READ(DCC);		switch (dcc & DCC_ADDRESSING_MODE_MASK) {		case DCC_ADDRESSING_MODE_SINGLE_CHANNEL:		case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC:			swizzle_x = I915_BIT_6_SWIZZLE_NONE;			swizzle_y = I915_BIT_6_SWIZZLE_NONE;			break;		case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED:			if (dcc & DCC_CHANNEL_XOR_DISABLE) {				/* This is the base swizzling by the GPU for				 * tiled buffers.				 */				swizzle_x = I915_BIT_6_SWIZZLE_9_10;				swizzle_y = I915_BIT_6_SWIZZLE_9;			} else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {				/* Bit 11 swizzling by the CPU in addition. */				swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;				swizzle_y = I915_BIT_6_SWIZZLE_9_11;			} else {				/* Bit 17 swizzling by the CPU in addition. */				swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;				swizzle_y = I915_BIT_6_SWIZZLE_9_17;			}			break;		}		if (dcc == 0xffffffff) {			DRM_ERROR("Couldn't read from MCHBAR.  "				  "Disabling tiling./n");			swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;			swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;		}	} else {		/* The 965, G33, and newer, have a very flexible memory		 * configuration.  It will enable dual-channel mode		 * (interleaving) on as much memory as it can, and the GPU		 * will additionally sometimes enable different bit 6		 * swizzling for tiled objects from the CPU.		 *		 * Here's what I found on the G965:		 *    slot fill         memory size  swizzling		 * 0A   0B   1A   1B    1-ch   2-ch		 * 512  0    0    0     512    0     O		 * 512  0    512  0     16     1008  X		 * 512  0    0    512   16     1008  X		 * 0    512  0    512   16     1008  X		 * 1024 1024 1024 0     2048   1024  O		 *		 * We could probably detect this based on either the DRB		 * matching, which was the case for the swizzling required in		 * the table above, or from the 1-ch value being less than		 * the minimum size of a rank.		 */		if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) {			swizzle_x = I915_BIT_6_SWIZZLE_NONE;			swizzle_y = I915_BIT_6_SWIZZLE_NONE;		} else {			swizzle_x = I915_BIT_6_SWIZZLE_9_10;			swizzle_y = I915_BIT_6_SWIZZLE_9;		}	}	dev_priv->mm.bit_6_swizzle_x = swizzle_x;	dev_priv->mm.bit_6_swizzle_y = swizzle_y;}

int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,			 u8 write_byte, u8 *read_byte){	struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;	struct radeon_i2c_chan *auxch = (struct radeon_i2c_chan *)adapter;	u16 address = algo_data->address;	u8 msg[5];	u8 reply[2];	unsigned retry;	int msg_bytes;	int reply_bytes = 1;	int ret;	u8 ack;	/* Set up the command byte */	if (mode & MODE_I2C_READ)		msg[2] = AUX_I2C_READ << 4;	else		msg[2] = AUX_I2C_WRITE << 4;	if (!(mode & MODE_I2C_STOP))		msg[2] |= AUX_I2C_MOT << 4;	msg[0] = address;	msg[1] = address >> 8;	switch (mode) {	case MODE_I2C_WRITE:		msg_bytes = 5;		msg[3] = msg_bytes << 4;		msg[4] = write_byte;		break;	case MODE_I2C_READ:		msg_bytes = 4;		msg[3] = msg_bytes << 4;		break;	default:		msg_bytes = 4;		msg[3] = 3 << 4;		break;	}	for (retry = 0; retry < 4; retry++) {		ret = radeon_process_aux_ch(auxch,					    msg, msg_bytes, reply, reply_bytes, 0, &ack);		if (ret == -EBUSY)			continue;		else if (ret < 0) {			DRM_DEBUG_KMS("aux_ch failed %d/n", ret);			return ret;		}		switch (ack & AUX_NATIVE_REPLY_MASK) {		case AUX_NATIVE_REPLY_ACK:			/* I2C-over-AUX Reply field is only valid			 * when paired with AUX ACK.			 */			break;		case AUX_NATIVE_REPLY_NACK:			DRM_DEBUG_KMS("aux_ch native nack/n");			return -EREMOTEIO;		case AUX_NATIVE_REPLY_DEFER:			DRM_DEBUG_KMS("aux_ch native defer/n");			udelay(400);			continue;		default:			DRM_ERROR("aux_ch invalid native reply 0x%02x/n", ack);			return -EREMOTEIO;		}		switch (ack & AUX_I2C_REPLY_MASK) {		case AUX_I2C_REPLY_ACK:			if (mode == MODE_I2C_READ)				*read_byte = reply[0];			return ret;		case AUX_I2C_REPLY_NACK:			DRM_DEBUG_KMS("aux_i2c nack/n");			return -EREMOTEIO;		case AUX_I2C_REPLY_DEFER:			DRM_DEBUG_KMS("aux_i2c defer/n");			udelay(400);			break;		default:			DRM_ERROR("aux_i2c invalid reply 0x%02x/n", ack);			return -EREMOTEIO;		}	}	DRM_DEBUG_KMS("aux i2c too many retries, giving up/n");	return -EREMOTEIO;}

static int armada_drm_load(struct drm_device *dev, unsigned long flags){	const struct platform_device_id *id;	const struct armada_variant *variant;	struct armada_private *priv;	struct resource *res[ARRAY_SIZE(priv->dcrtc)];	struct resource *mem = NULL;	int ret, n, i;	memset(res, 0, sizeof(res));	for (n = i = 0; ; n++) {		struct resource *r = platform_get_resource(dev->platformdev,							   IORESOURCE_MEM, n);		if (!r)			break;		/* Resources above 64K are graphics memory */		if (resource_size(r) > SZ_64K)			mem = r;		else if (i < ARRAY_SIZE(priv->dcrtc))			res[i++] = r;		else			return -EINVAL;	}	if (!mem)		return -ENXIO;	if (!devm_request_mem_region(dev->dev, mem->start,			resource_size(mem), "armada-drm"))		return -EBUSY;	priv = devm_kzalloc(dev->dev, sizeof(*priv), GFP_KERNEL);	if (!priv) {		DRM_ERROR("failed to allocate private/n");		return -ENOMEM;	}	platform_set_drvdata(dev->platformdev, dev);	dev->dev_private = priv;	/* Get the implementation specific driver data. */	id = platform_get_device_id(dev->platformdev);	if (!id)		return -ENXIO;	variant = (const struct armada_variant *)id->driver_data;	INIT_WORK(&priv->fb_unref_work, armada_drm_unref_work);	INIT_KFIFO(priv->fb_unref);	/* Mode setting support */	drm_mode_config_init(dev);	dev->mode_config.min_width = 320;	dev->mode_config.min_height = 200;	/*	 * With vscale enabled, the maximum width is 1920 due to the	 * 1920 by 3 lines RAM	 */	dev->mode_config.max_width = 1920;	dev->mode_config.max_height = 2048;	dev->mode_config.preferred_depth = 24;	dev->mode_config.funcs = &armada_drm_mode_config_funcs;	drm_mm_init(&priv->linear, mem->start, resource_size(mem));	/* Create all LCD controllers */	for (n = 0; n < ARRAY_SIZE(priv->dcrtc); n++) {		int irq;		if (!res[n])			break;		irq = platform_get_irq(dev->platformdev, n);		if (irq < 0)			goto err_kms;		ret = armada_drm_crtc_create(dev, dev->dev, res[n], irq,					     variant, NULL);		if (ret)			goto err_kms;	}	if (is_componentized(dev->dev)) {		ret = component_bind_all(dev->dev, dev);		if (ret)			goto err_kms;	} else {#ifdef CONFIG_DRM_ARMADA_TDA1998X		ret = armada_drm_connector_slave_create(dev, &tda19988_config);		if (ret)			goto err_kms;#endif	}	ret = drm_vblank_init(dev, dev->mode_config.num_crtc);	if (ret)		goto err_comp;//.........这里部分代码省略.........

static int enter_dsr_locked(struct mdfld_dsi_config *dsi_config, int level){	struct mdfld_dsi_hw_registers *regs;	struct mdfld_dsi_hw_context *ctx;	struct drm_psb_private *dev_priv;	struct drm_device *dev;	struct mdfld_dsi_pkg_sender *sender;	int err;	pm_message_t state;	PSB_DEBUG_ENTRY("mdfld_dsi_dsr: enter dsr/n");	if (!dsi_config)		return -EINVAL;	regs = &dsi_config->regs;	ctx = &dsi_config->dsi_hw_context;	dev = dsi_config->dev;	dev_priv = dev->dev_private;	sender = mdfld_dsi_get_pkg_sender(dsi_config);	if (!sender) {		DRM_ERROR("Failed to get dsi sender/n");		return -EINVAL;	}	if (level < DSR_EXITED) {		DRM_ERROR("Why to do this?");		return -EINVAL;	}	if (level > DSR_ENTERED_LEVEL0) {		/**		 * TODO: require OSPM interfaces to tell OSPM module that		 * display controller is ready to be power gated.		 * OSPM module needs to response this request ASAP.		 * NOTE: it makes no sense to have display controller islands		 * & pci power gated here directly. OSPM module is the only one		 * who can power gate/ungate power islands.		 * FIXME: since there's no ospm interfaces for acquiring		 * suspending DSI related power islands, we have to call OSPM		 * interfaces to power gate display islands and pci right now,		 * which should NOT happen in this way!!!		 */		if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,			OSPM_UHB_FORCE_POWER_ON)) {			DRM_ERROR("Failed power on display island/n");			return -EINVAL;		}		PSB_DEBUG_ENTRY("mdfld_dsi_dsr: entering DSR level 1/n");		err = mdfld_dsi_wait_for_fifos_empty(sender);		if (err) {			DRM_ERROR("mdfld_dsi_dsr: FIFO not empty/n");			ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);			return err;		}		ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);		/*suspend whole PCI host and related islands		** if failed at this try, revive te for another chance		*/		state.event = 0;		if (ospm_power_suspend()) {			/* Only display island is powered off then			 ** need revive the whole TE			 */			if (!ospm_power_is_hw_on(OSPM_DISPLAY_ISLAND))				exit_dsr_locked(dsi_config);			return -EINVAL;		}		/*		 *suspend pci		 *FIXME: should I do it here?		 *how about decoder/encoder is working??		 *OSPM should check the refcout of each islands before		 *actually power off PCI!!!		 *need invoke this in the same context, we need deal with		 *DSR lock later for suspend PCI may go to sleep!!!		 */		/*ospm_suspend_pci(dev->pdev);*/		PSB_DEBUG_ENTRY("mdfld_dsi_dsr: entered/n");		return 0;	}	PSB_DEBUG_ENTRY("mdfld_dsi_dsr: entering DSR level 0/n");	err = mdfld_dsi_wait_for_fifos_empty(sender);	if (err) {		DRM_ERROR("mdfld_dsi_dsr: FIFO not empty/n");		return err;	}	/*	 * To set the vblank_enabled to false with drm_vblank_off(), as	 * vblank_disable_and_save() would be scheduled late (<= 5s), and it	 * would cause drm_vblank_get() fail to turn on vsync interrupt//.........这里部分代码省略.........

static intvia_build_sg_info(drm_device_t *dev, drm_via_sg_info_t *vsg, drm_via_dmablit_t *xfer){	int draw = xfer->to_fb;	int ret = 0;		vsg->direction = (draw) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;	vsg->bounce_buffer = 0;	vsg->state = dr_via_sg_init;	if (xfer->num_lines <= 0 || xfer->line_length <= 0) {		DRM_ERROR("Zero size bitblt./n");		return DRM_ERR(EINVAL);	}	/*	 * Below check is a driver limitation, not a hardware one. We	 * don't want to lock unused pages, and don't want to incoporate the	 * extra logic of avoiding them. Make sure there are no. 	 * (Not a big limitation anyway.)	 */	if (((xfer->mem_stride - xfer->line_length) >= PAGE_SIZE) ||	    (xfer->mem_stride > 2048)) {		DRM_ERROR("Too large system memory stride./n");		return DRM_ERR(EINVAL);	}	if (xfer->num_lines > 2048) {		DRM_ERROR("Too many PCI DMA bitblt lines./n");		return DRM_ERR(EINVAL);	}			/* 	 * we allow a negative fb stride to allow flipping of images in	 * transfer. 	 */	if (xfer->mem_stride < xfer->line_length ||		abs(xfer->fb_stride) < xfer->line_length) {		DRM_ERROR("Invalid frame-buffer / memory stride./n");		return DRM_ERR(EINVAL);	}	/*	 * A hardware bug seems to be worked around if system memory addresses start on	 * 16 byte boundaries. This seems a bit restrictive however. VIA is contacted	 * about this. Meanwhile, impose the following restrictions:	 */#ifdef VIA_BUGFREE	if ((((unsigned long)xfer->mem_addr & 3) != ((unsigned long)xfer->fb_addr & 3)) ||	    ((xfer->mem_stride & 3) != (xfer->fb_stride & 3))) {		DRM_ERROR("Invalid DRM bitblt alignment./n");	        return DRM_ERR(EINVAL);	}#else	if ((((unsigned long)xfer->mem_addr & 15) || ((unsigned long)xfer->fb_addr & 15))) {		DRM_ERROR("Invalid DRM bitblt alignment./n");	        return DRM_ERR(EINVAL);	}	#endif	if (0 != (ret = via_lock_all_dma_pages(vsg, xfer))) {		DRM_ERROR("Could not lock DMA pages./n");		via_free_sg_info(dev->pdev, vsg);		return ret;	}	via_map_blit_for_device(dev->pdev, xfer, vsg, 0);	if (0 != (ret = via_alloc_desc_pages(vsg))) {		DRM_ERROR("Could not allocate DMA descriptor pages./n");		via_free_sg_info(dev->pdev, vsg);		return ret;	}	via_map_blit_for_device(dev->pdev, xfer, vsg, 1);		return 0;}

/* Test BO GTT->VRAM and VRAM->GTT GPU copies across the whole GTT aperture */void radeon_test_moves(struct radeon_device *rdev){	struct radeon_bo *vram_obj = NULL;	struct radeon_bo **gtt_obj = NULL;	struct radeon_fence *fence = NULL;	uint64_t gtt_addr, vram_addr;	unsigned i, n, size;	int r;	size = 1024 * 1024;	/* Number of tests =	 * (Total GTT - IB pool - writeback page - ring buffer) / test size	 */	n = (rdev->mc.gtt_size - RADEON_IB_POOL_SIZE*64*1024 - RADEON_GPU_PAGE_SIZE -	     rdev->cp.ring_size) / size;	gtt_obj = kzalloc(n * sizeof(*gtt_obj), GFP_KERNEL);	if (!gtt_obj) {		DRM_ERROR("Failed to allocate %d pointers/n", n);		r = 1;		goto out_cleanup;	}	r = radeon_bo_create(rdev, NULL, size, true, RADEON_GEM_DOMAIN_VRAM,				&vram_obj);	if (r) {		DRM_ERROR("Failed to create VRAM object/n");		goto out_cleanup;	}	r = radeon_bo_reserve(vram_obj, false);	if (unlikely(r != 0))		goto out_cleanup;	r = radeon_bo_pin(vram_obj, RADEON_GEM_DOMAIN_VRAM, &vram_addr);	if (r) {		DRM_ERROR("Failed to pin VRAM object/n");		goto out_cleanup;	}	for (i = 0; i < n; i++) {		void *gtt_map, *vram_map;		void **gtt_start, **gtt_end;		void **vram_start, **vram_end;		r = radeon_bo_create(rdev, NULL, size, true,					 RADEON_GEM_DOMAIN_GTT, gtt_obj + i);		if (r) {			DRM_ERROR("Failed to create GTT object %d/n", i);			goto out_cleanup;		}		r = radeon_bo_reserve(gtt_obj[i], false);		if (unlikely(r != 0))			goto out_cleanup;		r = radeon_bo_pin(gtt_obj[i], RADEON_GEM_DOMAIN_GTT, &gtt_addr);		if (r) {			DRM_ERROR("Failed to pin GTT object %d/n", i);			goto out_cleanup;		}		r = radeon_bo_kmap(gtt_obj[i], &gtt_map);		if (r) {			DRM_ERROR("Failed to map GTT object %d/n", i);			goto out_cleanup;		}		for (gtt_start = gtt_map, gtt_end = gtt_map + size;		     gtt_start < gtt_end;		     gtt_start++)			*gtt_start = gtt_start;		radeon_bo_kunmap(gtt_obj[i]);		r = radeon_fence_create(rdev, &fence);		if (r) {			DRM_ERROR("Failed to create GTT->VRAM fence %d/n", i);			goto out_cleanup;		}		r = radeon_copy(rdev, gtt_addr, vram_addr, size / RADEON_GPU_PAGE_SIZE, fence);		if (r) {			DRM_ERROR("Failed GTT->VRAM copy %d/n", i);			goto out_cleanup;		}		r = radeon_fence_wait(fence, false);		if (r) {			DRM_ERROR("Failed to wait for GTT->VRAM fence %d/n", i);			goto out_cleanup;		}		radeon_fence_unref(&fence);		r = radeon_bo_kmap(vram_obj, &vram_map);		if (r) {			DRM_ERROR("Failed to map VRAM object after copy %d/n", i);			goto out_cleanup;		}		for (gtt_start = gtt_map, gtt_end = gtt_map + size,//.........这里部分代码省略.........

/** * i965_reset - reset chip after a hang * @dev: drm device to reset * @flags: reset domains * * Reset the chip.  Useful if a hang is detected. Returns zero on successful * reset or otherwise an error code. * * Procedure is fairly simple: *   - reset the chip using the reset reg *   - re-init context state *   - re-init hardware status page *   - re-init ring buffer *   - re-init interrupt state *   - re-init display */int i965_reset(struct drm_device *dev, u8 flags){	drm_i915_private_t *dev_priv = dev->dev_private;	unsigned long timeout;	u8 gdrst;	/*	 * We really should only reset the display subsystem if we actually	 * need to	 */	bool need_display = true;	mutex_lock(&dev->struct_mutex);	/*	 * Clear request list	 */	i915_gem_retire_requests(dev, &dev_priv->render_ring);	if (need_display)		i915_save_display(dev);	if (IS_I965G(dev) || IS_G4X(dev)) {		/*		 * Set the domains we want to reset, then the reset bit (bit 0).		 * Clear the reset bit after a while and wait for hardware status		 * bit (bit 1) to be set		 */		pci_read_config_byte(dev->pdev, GDRST, &gdrst);		pci_write_config_byte(dev->pdev, GDRST, gdrst | flags | ((flags == GDRST_FULL) ? 0x1 : 0x0));		udelay(50);		pci_write_config_byte(dev->pdev, GDRST, gdrst & 0xfe);		/* ...we don't want to loop forever though, 500ms should be plenty */	       timeout = jiffies + msecs_to_jiffies(500);		do {			udelay(100);			pci_read_config_byte(dev->pdev, GDRST, &gdrst);		} while ((gdrst & 0x1) && time_after(timeout, jiffies));		if (gdrst & 0x1) {			WARN(true, "i915: Failed to reset chip/n");			mutex_unlock(&dev->struct_mutex);			return -EIO;		}	} else {		DRM_ERROR("Error occurred. Don't know how to reset this chip./n");		mutex_unlock(&dev->struct_mutex);		return -ENODEV;	}	/* Ok, now get things going again... */	/*	 * Everything depends on having the GTT running, so we need to start	 * there.  Fortunately we don't need to do this unless we reset the	 * chip at a PCI level.	 *	 * Next we need to restore the context, but we don't use those	 * yet either...	 *	 * Ring buffer needs to be re-initialized in the KMS case, or if X	 * was running at the time of the reset (i.e. we weren't VT	 * switched away).	 */	if (drm_core_check_feature(dev, DRIVER_MODESET) ||			!dev_priv->mm.suspended) {		struct intel_ring_buffer *ring = &dev_priv->render_ring;		dev_priv->mm.suspended = 0;		ring->init(dev, ring);		mutex_unlock(&dev->struct_mutex);		drm_irq_uninstall(dev);		drm_irq_install(dev);		mutex_lock(&dev->struct_mutex);	}	/*	 * Display needs restore too...	 */	if (need_display)		i915_restore_display(dev);	mutex_unlock(&dev->struct_mutex);	return 0;}

void mdfld_dsi_dpi_controller_init(struct mdfld_dsi_config *dsi_config,								int pipe){	struct drm_device *dev = dsi_config->dev;	int lane_count = dsi_config->lane_count;	struct mdfld_dsi_dpi_timing dpi_timing;	struct drm_display_mode *mode = dsi_config->mode;	u32 val;	/*un-ready device*/	REG_FLD_MOD(MIPI_DEVICE_READY_REG(pipe), 0, 0, 0);	/*init dsi adapter before kicking off*/	REG_WRITE(MIPI_CTRL_REG(pipe), 0x00000018);	/*enable all interrupts*/	REG_WRITE(MIPI_INTR_EN_REG(pipe), 0xffffffff);	/*set up func_prg*/	val = lane_count;	val |= dsi_config->channel_num << DSI_DPI_VIRT_CHANNEL_OFFSET;	switch (dsi_config->bpp) {	case 16:		val |= DSI_DPI_COLOR_FORMAT_RGB565;		break;	case 18:		val |= DSI_DPI_COLOR_FORMAT_RGB666;		break;	case 24:		val |= DSI_DPI_COLOR_FORMAT_RGB888;		break;	default:		DRM_ERROR("unsupported color format, bpp = %d/n",							dsi_config->bpp);	}	REG_WRITE(MIPI_DSI_FUNC_PRG_REG(pipe), val);	REG_WRITE(MIPI_HS_TX_TIMEOUT_REG(pipe),			(mode->vtotal * mode->htotal * dsi_config->bpp /				(8 * lane_count)) & DSI_HS_TX_TIMEOUT_MASK);	REG_WRITE(MIPI_LP_RX_TIMEOUT_REG(pipe),				0xffff & DSI_LP_RX_TIMEOUT_MASK);	/*max value: 20 clock cycles of txclkesc*/	REG_WRITE(MIPI_TURN_AROUND_TIMEOUT_REG(pipe),				0x14 & DSI_TURN_AROUND_TIMEOUT_MASK);	/*min 21 txclkesc, max: ffffh*/	REG_WRITE(MIPI_DEVICE_RESET_TIMER_REG(pipe),				0xffff & DSI_RESET_TIMER_MASK);	REG_WRITE(MIPI_DPI_RESOLUTION_REG(pipe),				mode->vdisplay << 16 | mode->hdisplay);	/*set DPI timing registers*/	mdfld_dsi_dpi_timing_calculation(mode, &dpi_timing,				dsi_config->lane_count, dsi_config->bpp);	REG_WRITE(MIPI_HSYNC_COUNT_REG(pipe),			dpi_timing.hsync_count & DSI_DPI_TIMING_MASK);	REG_WRITE(MIPI_HBP_COUNT_REG(pipe),			dpi_timing.hbp_count & DSI_DPI_TIMING_MASK);	REG_WRITE(MIPI_HFP_COUNT_REG(pipe),			dpi_timing.hfp_count & DSI_DPI_TIMING_MASK);	REG_WRITE(MIPI_HACTIVE_COUNT_REG(pipe),			dpi_timing.hactive_count & DSI_DPI_TIMING_MASK);	REG_WRITE(MIPI_VSYNC_COUNT_REG(pipe),			dpi_timing.vsync_count & DSI_DPI_TIMING_MASK);	REG_WRITE(MIPI_VBP_COUNT_REG(pipe),			dpi_timing.vbp_count & DSI_DPI_TIMING_MASK);	REG_WRITE(MIPI_VFP_COUNT_REG(pipe),			dpi_timing.vfp_count & DSI_DPI_TIMING_MASK);	REG_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT_REG(pipe), 0x46);	/*min: 7d0 max: 4e20*/	REG_WRITE(MIPI_INIT_COUNT_REG(pipe), 0x000007d0);	/*set up video mode*/	val = dsi_config->video_mode | DSI_DPI_COMPLETE_LAST_LINE;	REG_WRITE(MIPI_VIDEO_MODE_FORMAT_REG(pipe), val);	REG_WRITE(MIPI_EOT_DISABLE_REG(pipe), 0x00000000);	REG_WRITE(MIPI_LP_BYTECLK_REG(pipe), 0x00000004);	/*TODO: figure out how to setup these registers*/	if (mdfld_get_panel_type(dev, pipe) == TC35876X)		REG_WRITE(MIPI_DPHY_PARAM_REG(pipe), 0x2A0c6008);	else		REG_WRITE(MIPI_DPHY_PARAM_REG(pipe), 0x150c3408);	REG_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT_REG(pipe), (0xa << 16) | 0x14);	if (mdfld_get_panel_type(dev, pipe) == TC35876X)		tc35876x_set_bridge_reset_state(dev, 0);  /*Pull High Reset */	/*set device ready*/	REG_FLD_MOD(MIPI_DEVICE_READY_REG(pipe), 1, 0, 0);//.........这里部分代码省略.........

/** * radeon_info_ioctl - answer a device specific request. * * @rdev: radeon device pointer * @data: request object * @filp: drm filp * * This function is used to pass device specific parameters to the userspace * drivers.  Examples include: pci device id, pipeline parms, tiling params, * etc. (all asics). * Returns 0 on success, -EINVAL on failure. */static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp){	struct radeon_device *rdev = dev->dev_private;	struct drm_radeon_info *info = data;	struct radeon_mode_info *minfo = &rdev->mode_info;	uint32_t *value, value_tmp, *value_ptr, value_size;	uint64_t value64;	struct drm_crtc *crtc;	int i, found;	value_ptr = (uint32_t *)((unsigned long)info->value);	value = &value_tmp;	value_size = sizeof(uint32_t);	switch (info->request) {	case RADEON_INFO_DEVICE_ID:		*value = dev->pdev->device;		break;	case RADEON_INFO_NUM_GB_PIPES:		*value = rdev->num_gb_pipes;		break;	case RADEON_INFO_NUM_Z_PIPES:		*value = rdev->num_z_pipes;		break;	case RADEON_INFO_ACCEL_WORKING:		/* xf86-video-ati 6.13.0 relies on this being false for evergreen */		if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))			*value = false;		else			*value = rdev->accel_working;		break;	case RADEON_INFO_CRTC_FROM_ID:		if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {			DRM_ERROR("copy_from_user %s:%u/n", __func__, __LINE__);			return -EFAULT;		}		for (i = 0, found = 0; i < rdev->num_crtc; i++) {			crtc = (struct drm_crtc *)minfo->crtcs[i];			if (crtc && crtc->base.id == *value) {				struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);				*value = radeon_crtc->crtc_id;				found = 1;				break;			}		}		if (!found) {			DRM_DEBUG_KMS("unknown crtc id %d/n", *value);			return -EINVAL;		}		break;	case RADEON_INFO_ACCEL_WORKING2:		*value = rdev->accel_working;		break;	case RADEON_INFO_TILING_CONFIG:		if (rdev->family >= CHIP_BONAIRE)			*value = rdev->config.cik.tile_config;		else if (rdev->family >= CHIP_TAHITI)			*value = rdev->config.si.tile_config;		else if (rdev->family >= CHIP_CAYMAN)			*value = rdev->config.cayman.tile_config;		else if (rdev->family >= CHIP_CEDAR)			*value = rdev->config.evergreen.tile_config;		else if (rdev->family >= CHIP_RV770)			*value = rdev->config.rv770.tile_config;		else if (rdev->family >= CHIP_R600)			*value = rdev->config.r600.tile_config;		else {			DRM_DEBUG_KMS("tiling config is r6xx+ only!/n");			return -EINVAL;		}		break;	case RADEON_INFO_WANT_HYPERZ:		/* The "value" here is both an input and output parameter.		 * If the input value is 1, filp requests hyper-z access.		 * If the input value is 0, filp revokes its hyper-z access.		 *		 * When returning, the value is 1 if filp owns hyper-z access,		 * 0 otherwise. */		if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {			DRM_ERROR("copy_from_user %s:%u/n", __func__, __LINE__);			return -EFAULT;		}		if (*value >= 2) {			DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d/n", *value);			return -EINVAL;		}		radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);		break;//.........这里部分代码省略.........

int mdfld_panel_generic_dsi_dbi_set_power(struct drm_encoder *encoder, bool on){	int ret = 0;	struct mdfld_dsi_encoder *dsi_encoder = MDFLD_DSI_ENCODER(encoder);	struct mdfld_dsi_dbi_output *dbi_output =		MDFLD_DSI_DBI_OUTPUT(dsi_encoder);	struct panel_funcs *p_funcs = dbi_output->p_funcs;	struct mdfld_dsi_connector *dsi_connector =		mdfld_dsi_encoder_get_connector(dsi_encoder);	struct mdfld_dsi_config *dsi_config =		mdfld_dsi_encoder_get_config(dsi_encoder);	struct drm_device *dev = encoder->dev;	struct drm_psb_private *dev_priv = dev->dev_private;	u32 reg_offset = 0;	int pipe = (dbi_output->channel_num == 0) ? 0 : 2;	PSB_DEBUG_ENTRY("pipe %d : %s, panel on: %s/n", pipe, on ? "On" : "Off",			dbi_output->dbi_panel_on ? "True" : "False");	if (pipe == 2) {		if (on)			dev_priv->dual_mipi = true;		else			dev_priv->dual_mipi = false;		reg_offset = MIPIC_REG_OFFSET;	} else {		if (!on)			dev_priv->dual_mipi = false;	}	if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,				OSPM_UHB_FORCE_POWER_ON)) {		DRM_ERROR("hw begin failed/n");		return -EAGAIN;	}	mutex_lock(&dsi_config->context_lock);	if (on) {		if (dbi_output->dbi_panel_on)			goto out_err;		ret = mdfld_panel_generic_dsi_dbi_power_on(encoder);		if (ret) {			DRM_ERROR("power on error/n");			goto out_err;		}		dbi_output->dbi_panel_on = true;		if (pipe == 2)			dev_priv->dbi_panel_on2 = true;		else			dev_priv->dbi_panel_on = true;		if (dev_priv->platform_rev_id != MDFLD_PNW_A0)			mdfld_enable_te(dev, pipe);		/* wake up error detector if ESD enabled */		if (p_funcs->esd_detection)			mdfld_dsi_error_detector_wakeup(dsi_connector);		else			PSB_DEBUG_ENTRY("ESD detection disabled/n");		dsi_config->dsi_hw_context.panel_on = 1;	} else {		if (!dbi_output->dbi_panel_on && !dbi_output->first_boot)			goto out_err;		dbi_output->dbi_panel_on = false;		dbi_output->first_boot = false;		if (pipe == 2)			dev_priv->dbi_panel_on2 = false;		else			dev_priv->dbi_panel_on = false;		if (dev_priv->platform_rev_id != MDFLD_PNW_A0)			mdfld_disable_te(dev, pipe);		ret = mdfld_panel_generic_dsi_dbi_power_off(encoder);		if (ret) {			DRM_ERROR("power on error/n");			goto out_err;		}		dsi_config->dsi_hw_context.panel_on = 0;	}out_err:	mutex_unlock(&dsi_config->context_lock);	ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);	if (ret)		DRM_ERROR("failed/n");	else		PSB_DEBUG_ENTRY("successfully/n");	return ret;//.........这里部分代码省略.........

//.........这里部分代码省略.........	mode->hsync_start = mode->hdisplay + 10;	mode->hsync_end = mode->hsync_start + 10;	mode->htotal = mode->hsync_end + 20;	/* VFP = 10, VSYNC = 2, VBP = 20 */	mode->vsync_start = mode->vdisplay + 10;	mode->vsync_end = mode->vsync_start + 2;	mode->vtotal = mode->vsync_end + 10;	mode->vrefresh = 60;	mode->clock = mode->vrefresh * mode->vtotal *		mode->htotal / 1000;	drm_mode_set_name(mode);	drm_mode_set_crtcinfo(mode, 0);	mode->type |= DRM_MODE_TYPE_PREFERRED;	return mode;}staticint __gi_renesas_dsi_power_on(struct mdfld_dsi_config *dsi_config){	struct drm_device *dev = dsi_config->dev;	struct drm_psb_private *dev_priv = dev->dev_private;	struct mdfld_dsi_hw_registers *regs =		&dsi_config->regs;	struct mdfld_dsi_pkg_sender *sender =		mdfld_dsi_get_pkg_sender(dsi_config);	int err = 0;	PSB_DEBUG_ENTRY("/n");	if (!sender) {		DRM_ERROR("Failed to get DSI packet sender/n");		return -EINVAL;	}	if (drm_psb_enable_cabc) {		/* enable cabc */		gi_er61529_backlight_cntr_1[1] = 0x01;		mdfld_dsi_send_gen_long_hs(sender, gi_er61529_mcs_protect_on, 2, 0);		mdfld_dsi_send_gen_long_hs(sender, gi_er61529_backlight_cntr_1, 21, 0);		mdfld_dsi_send_gen_long_hs(sender, gi_er61529_mcs_protect_off, 2, 0);	}	mdfld_dsi_send_gen_long_hs(sender, gi_er61529_mcs_protect_on, 2, 0);	mdfld_dsi_send_gen_long_hs(sender, gi_er61529_backlight_cntr, 5, 0);	mdfld_dsi_send_gen_long_hs(sender, gi_er61529_mcs_protect_off, 2, 0);	mdfld_dsi_send_mcs_long_hs(sender, gi_er61529_exit_sleep_mode, 1, 0);	mdelay(120);	mdfld_dsi_send_mcs_long_hs(sender, gi_er61529_set_tear_on, 2, 0);	mdfld_dsi_send_mcs_long_hs(sender, gi_er61529_dcs_set_display_on, 1, 0);	return err;}staticint __gi_renesas_dsi_power_off(struct mdfld_dsi_config *dsi_config){	struct mdfld_dsi_pkg_sender *sender =		mdfld_dsi_get_pkg_sender(dsi_config);	int err = 0;	PSB_DEBUG_ENTRY("Turn off video mode TMD panel.../n");	if (!sender) {

//.........这里部分代码省略.........				  FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);	/* Enable the PCH Receiver FDI PLL */	rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |		     FDI_RX_PLL_ENABLE | ((intel_crtc->fdi_lanes - 1) << 19);	I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);	POSTING_READ(_FDI_RXA_CTL);	udelay(220);	/* Switch from Rawclk to PCDclk */	rx_ctl_val |= FDI_PCDCLK;	I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);	/* Configure Port Clock Select */	I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);	/* Start the training iterating through available voltages and emphasis,	 * testing each value twice. */	for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) {		/* Configure DP_TP_CTL with auto-training */		I915_WRITE(DP_TP_CTL(PORT_E),					DP_TP_CTL_FDI_AUTOTRAIN |					DP_TP_CTL_ENHANCED_FRAME_ENABLE |					DP_TP_CTL_LINK_TRAIN_PAT1 |					DP_TP_CTL_ENABLE);		/* Configure and enable DDI_BUF_CTL for DDI E with next voltage.		 * DDI E does not support port reversal, the functionality is		 * achieved on the PCH side in FDI_RX_CTL, so no need to set the		 * port reversal bit */		I915_WRITE(DDI_BUF_CTL(PORT_E),			   DDI_BUF_CTL_ENABLE |			   ((intel_crtc->fdi_lanes - 1) << 1) |			   hsw_ddi_buf_ctl_values[i / 2]);		POSTING_READ(DDI_BUF_CTL(PORT_E));		udelay(600);		/* Program PCH FDI Receiver TU */		I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));		/* Enable PCH FDI Receiver with auto-training */		rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;		I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);		POSTING_READ(_FDI_RXA_CTL);		/* Wait for FDI receiver lane calibration */		udelay(30);		/* Unset FDI_RX_MISC pwrdn lanes */		temp = I915_READ(_FDI_RXA_MISC);		temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);		I915_WRITE(_FDI_RXA_MISC, temp);		POSTING_READ(_FDI_RXA_MISC);		/* Wait for FDI auto training time */		udelay(5);		temp = I915_READ(DP_TP_STATUS(PORT_E));		if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {			DRM_DEBUG_KMS("FDI link training done on step %d/n", i);			/* Enable normal pixel sending for FDI */			I915_WRITE(DP_TP_CTL(PORT_E),				   DP_TP_CTL_FDI_AUTOTRAIN |				   DP_TP_CTL_LINK_TRAIN_NORMAL |				   DP_TP_CTL_ENHANCED_FRAME_ENABLE |				   DP_TP_CTL_ENABLE);			return;		}		temp = I915_READ(DDI_BUF_CTL(PORT_E));		temp &= ~DDI_BUF_CTL_ENABLE;		I915_WRITE(DDI_BUF_CTL(PORT_E), temp);		POSTING_READ(DDI_BUF_CTL(PORT_E));		/* Disable DP_TP_CTL and FDI_RX_CTL and retry */		temp = I915_READ(DP_TP_CTL(PORT_E));		temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);		temp |= DP_TP_CTL_LINK_TRAIN_PAT1;		I915_WRITE(DP_TP_CTL(PORT_E), temp);		POSTING_READ(DP_TP_CTL(PORT_E));		intel_wait_ddi_buf_idle(dev_priv, PORT_E);		rx_ctl_val &= ~FDI_RX_ENABLE;		I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);		POSTING_READ(_FDI_RXA_CTL);		/* Reset FDI_RX_MISC pwrdn lanes */		temp = I915_READ(_FDI_RXA_MISC);		temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);		temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);		I915_WRITE(_FDI_RXA_MISC, temp);		POSTING_READ(_FDI_RXA_MISC);	}	DRM_ERROR("FDI link training failed!/n");}