自学教程：C++ DSSDBG函数代码示例

static void dss_early_suspend(struct early_suspend *h){	DSSDBG("%s/n", __func__);	dss_suspend_all_devices();}

static void dss_late_resume(struct early_suspend *h){	DSSDBG("%s/n", __func__);	dss_resume_all_devices();}

int hdmi_audio_enable(void){	DSSDBG("audio_enable/n");	return hdmi.ip_data.ops->audio_enable(&hdmi.ip_data);}

/* Check if overlay parameters are compatible with display */int dss_check_overlay(struct omap_overlay *ovl, struct omap_dss_device *dssdev){	struct omap_overlay_info *info;	u16 outw, outh;	u16 dw, dh;	if (!dssdev)		return 0;	if (!ovl->info.enabled)		return 0;	info = &ovl->info;	if (info->paddr == 0) {		DSSDBG("check_overlay failed: paddr 0/n");		return -EINVAL;	}	dssdev->driver->get_resolution(dssdev, &dw, &dh);	/* y resolution to be doubled in case of interlaced HDMI */	if ((ovl->info.field == IBUF_IDEV) || (ovl->info.field == PBUF_IDEV))		dh *= 2;	DSSDBG("check_overlay %d: (%d,%d %dx%d -> %dx%d) disp (%dx%d)/n",			ovl->id,			info->pos_x, info->pos_y,			info->width, info->height,			info->out_width, info->out_height,			dw, dh);	if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0) {		outw = info->width;		outh = info->height;	} else {		if (info->out_width == 0)			outw = info->width;		else			outw = info->out_width;		if (info->out_height == 0)			outh = info->height;		else			outh = info->out_height;	}	if ((dw < info->pos_x + outw) && !info->out_wb) {		DSSDBG("check_overlay failed 1: %d < %d + %d/n",				dw, info->pos_x, outw);		return -EINVAL;	}	if ((dh < info->pos_y + outh) && !info->out_wb) {		DSSDBG("check_overlay failed 2: %d < %d + %d/n",				dh, info->pos_y, outh);		return -EINVAL;	}	if ((ovl->supported_modes & info->color_mode) == 0) {		DSSERR("overlay doesn't support mode %d/n", info->color_mode);		return -EINVAL;	}	if ((info->zorder < OMAP_DSS_OVL_ZORDER_0) ||			(info->zorder > OMAP_DSS_OVL_ZORDER_3)) {		DSSERR("overlay doesn't support zorder %d/n", info->zorder);		return -EINVAL;	}	return 0;}

void hdmi_audio_stop(void){	DSSDBG("audio_stop/n");	hdmi.ip_data.ops->audio_stop(&hdmi.ip_data);}

int hdmi_audio_start(void){	DSSDBG("audio_start/n");	return hdmi.ip_data.ops->audio_start(&hdmi.ip_data);}

void hdmi_audio_disable(void){	DSSDBG("audio_disable/n");	hdmi.ip_data.ops->audio_disable(&hdmi.ip_data);}

static int hdmi_power_on_full(struct omap_dss_device *dssdev){	int r;	struct omap_video_timings *p;	enum omap_channel channel = dssdev->dispc_channel;	struct hdmi_wp_data *wp = &hdmi.wp;	struct dss_pll_clock_info hdmi_cinfo = { 0 };	unsigned pc;	r = hdmi_power_on_core(dssdev);	if (r)		return r;	/* disable and clear irqs */	hdmi_wp_clear_irqenable(wp, 0xffffffff);	hdmi_wp_set_irqstatus(wp, 0xffffffff);	p = &hdmi.cfg.timings;	DSSDBG("hdmi_power_on x_res= %d y_res = %d/n", p->x_res, p->y_res);	pc = p->pixelclock;	if (p->double_pixel)		pc *= 2;	hdmi_pll_compute(&hdmi.pll, pc, &hdmi_cinfo);	r = dss_pll_enable(&hdmi.pll.pll);	if (r) {		DSSERR("Failed to enable PLL/n");		goto err_pll_enable;	}	r = dss_pll_set_config(&hdmi.pll.pll, &hdmi_cinfo);	if (r) {		DSSERR("Failed to configure PLL/n");		goto err_pll_cfg;	}	r = hdmi_phy_configure(&hdmi.phy, hdmi_cinfo.clkdco,		hdmi_cinfo.clkout[0]);	if (r) {		DSSDBG("Failed to configure PHY/n");		goto err_phy_cfg;	}	r = hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);	if (r)		goto err_phy_pwr;	hdmi4_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg);	/* bypass TV gamma table */	dispc_enable_gamma_table(0);	/* tv size */	dss_mgr_set_timings(channel, p);	r = dss_mgr_enable(channel);	if (r)		goto err_mgr_enable;	r = hdmi_wp_video_start(&hdmi.wp);	if (r)		goto err_vid_enable;	hdmi_wp_set_irqenable(wp,		HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT);	return 0;err_vid_enable:	dss_mgr_disable(channel);err_mgr_enable:	hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);err_phy_pwr:err_phy_cfg:err_pll_cfg:	dss_pll_disable(&hdmi.pll.pll);err_pll_enable:	hdmi_power_off_core(dssdev);	return -EIO;}

static ssize_t overlay_manager_store(struct omap_overlay *ovl, const char *buf,		size_t size){	int i, r;	struct omap_overlay_manager *mgr = NULL;	struct omap_overlay_manager *old_mgr;	int len = size;	if (buf[size-1] == '/n')		--len;	if (len > 0) {		for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {			mgr = omap_dss_get_overlay_manager(i);			if (sysfs_streq(buf, mgr->name))				break;			mgr = NULL;		}	}	if (len > 0 && mgr == NULL)		return -EINVAL;	if (mgr)		DSSDBG("manager %s found/n", mgr->name);	if (mgr == ovl->manager)		return size;	old_mgr = ovl->manager;	r = dispc_runtime_get();	if (r)		return r;	/* detach old manager */	if (old_mgr) {		r = ovl->unset_manager(ovl);		if (r) {			DSSERR("detach failed/n");			goto err;		}		r = old_mgr->apply(old_mgr);		if (r)			goto err;	}	if (mgr) {		r = ovl->set_manager(ovl, mgr);		if (r) {			DSSERR("Failed to attach overlay/n");			goto err;		}		r = mgr->apply(mgr);		if (r)			goto err;	}	dispc_runtime_put();	return size;err:	dispc_runtime_put();	return r;}

//.........这里部分代码省略.........	case 9:		parallelmode = OMAP_DSS_RFBI_PARALLELMODE_9;		break;	case 12:		parallelmode = OMAP_DSS_RFBI_PARALLELMODE_12;		break;	case 16:		parallelmode = OMAP_DSS_RFBI_PARALLELMODE_16;		break;	default:		BUG();		return 1;	}	rfbi.parallelmode = parallelmode;	if ((bpp % lines) == 0) {		switch (bpp / lines) {		case 1:			cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_1_1;			break;		case 2:			cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_2_1;			break;		case 3:			cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_3_1;			break;		default:			BUG();			return 1;		}	} else if ((2 * bpp % lines) == 0) {		if ((2 * bpp / lines) == 3)			cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_3_2;		else {			BUG();			return 1;		}	} else {		BUG();		return 1;	}	switch (cycleformat) {	case OMAP_DSS_RFBI_CYCLEFORMAT_1_1:		cycle1 = lines;		break;	case OMAP_DSS_RFBI_CYCLEFORMAT_2_1:		cycle1 = lines;		cycle2 = lines;		break;	case OMAP_DSS_RFBI_CYCLEFORMAT_3_1:		cycle1 = lines;		cycle2 = lines;		cycle3 = lines;		break;	case OMAP_DSS_RFBI_CYCLEFORMAT_3_2:		cycle1 = lines;		cycle2 = (lines / 2) | ((lines / 2) << 16);		cycle3 = (lines << 16);		break;	}	REG_FLD_MOD(RFBI_CONTROL, 0, 3, 2); /* clear CS */	l = 0;	l |= FLD_VAL(parallelmode, 1, 0);	l |= FLD_VAL(0, 3, 2);		/* TRIGGERMODE: ITE */	l |= FLD_VAL(0, 4, 4);		/* TIMEGRANULARITY */	l |= FLD_VAL(datatype, 6, 5);	/* l |= FLD_VAL(2, 8, 7); */	/* L4FORMAT, 2pix/L4 */	l |= FLD_VAL(0, 8, 7);	/* L4FORMAT, 1pix/L4 */	l |= FLD_VAL(cycleformat, 10, 9);	l |= FLD_VAL(0, 12, 11);	/* UNUSEDBITS */	l |= FLD_VAL(0, 16, 16);	/* A0POLARITY */	l |= FLD_VAL(0, 17, 17);	/* REPOLARITY */	l |= FLD_VAL(0, 18, 18);	/* WEPOLARITY */	l |= FLD_VAL(0, 19, 19);	/* CSPOLARITY */	l |= FLD_VAL(1, 20, 20);	/* TE_VSYNC_POLARITY */	l |= FLD_VAL(1, 21, 21);	/* HSYNCPOLARITY */	rfbi_write_reg(RFBI_CONFIG(rfbi_module), l);	rfbi_write_reg(RFBI_DATA_CYCLE1(rfbi_module), cycle1);	rfbi_write_reg(RFBI_DATA_CYCLE2(rfbi_module), cycle2);	rfbi_write_reg(RFBI_DATA_CYCLE3(rfbi_module), cycle3);	l = rfbi_read_reg(RFBI_CONTROL);	l = FLD_MOD(l, rfbi_module+1, 3, 2); /* Select CSx */	l = FLD_MOD(l, 0, 1, 1); /* clear bypass */	rfbi_write_reg(RFBI_CONTROL, l);	DSSDBG("RFBI config: bpp %d, lines %d, cycles: 0x%x 0x%x 0x%x/n",	       bpp, lines, cycle1, cycle2, cycle3);	return 0;}

static int hdmi_power_on_full(struct omap_dss_device *dssdev){	int r;	struct omap_video_timings *p;	struct omap_overlay_manager *mgr = hdmi.output.manager;	struct dss_pll_clock_info hdmi_cinfo = { 0 };	r = hdmi_power_on_core(dssdev);	if (r)		return r;	p = &hdmi.cfg.timings;	DSSDBG("hdmi_power_on x_res= %d y_res = %d/n", p->x_res, p->y_res);	hdmi_pll_compute(&hdmi.pll, p->pixelclock, &hdmi_cinfo);	/* disable and clear irqs */	hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);	hdmi_wp_set_irqstatus(&hdmi.wp,			hdmi_wp_get_irqstatus(&hdmi.wp));	r = dss_pll_enable(&hdmi.pll.pll);	if (r) {		DSSERR("Failed to enable PLL/n");		goto err_pll_enable;	}	r = dss_pll_set_config(&hdmi.pll.pll, &hdmi_cinfo);	if (r) {		DSSERR("Failed to configure PLL/n");		goto err_pll_cfg;	}	r = hdmi_phy_configure(&hdmi.phy, hdmi_cinfo.clkdco,		hdmi_cinfo.clkout[0]);	if (r) {		DSSDBG("Failed to start PHY/n");		goto err_phy_cfg;	}	r = hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_LDOON);	if (r)		goto err_phy_pwr;	hdmi5_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg);	/* bypass TV gamma table */	dispc_enable_gamma_table(0);	/* tv size */	dss_mgr_set_timings(mgr, p);	r = hdmi_wp_video_start(&hdmi.wp);	if (r)		goto err_vid_enable;	r = dss_mgr_enable(mgr);	if (r)		goto err_mgr_enable;	hdmi_wp_set_irqenable(&hdmi.wp,			HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT);	return 0;err_mgr_enable:	hdmi_wp_video_stop(&hdmi.wp);err_vid_enable:	hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);err_phy_pwr:err_phy_cfg:err_pll_cfg:	dss_pll_disable(&hdmi.pll.pll);err_pll_enable:	hdmi_power_off_core(dssdev);	return -EIO;}

static ssize_t overlay_manager_store(struct omap_overlay *ovl, const char *buf,		size_t size){	int i, r;	struct omap_overlay_manager *mgr = NULL;	struct omap_overlay_manager *old_mgr;	struct omap_overlay_info info;	int len = size;	if (buf[size-1] == '/n')		--len;	if (len > 0) {		for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {			mgr = omap_dss_get_overlay_manager(i);			if (!mgr) {				WARN_ON(1);				continue;			}			if (strncmp(buf, mgr->name, len) == 0)				break;			mgr = NULL;		}	}	if (len > 0 && mgr == NULL)		return -EINVAL;	if (mgr)		DSSDBG("manager %s found/n", mgr->name);	if (mgr == ovl->manager)		return size;	if (mgr && sysfs_streq(mgr->name, "tv")) {		ovl->get_overlay_info(ovl, &info);		if (mgr->device->panel.timings.x_res < info.width ||			mgr->device->panel.timings.y_res < info.height) {			printk(KERN_ERR"TV does not support downscaling"			"Please configure overlay to supported format");			return -EINVAL;		}	}	old_mgr = ovl->manager;	/* detach old manager */	if (old_mgr) {		r = ovl->unset_manager(ovl);		if (r) {			DSSERR("detach failed/n");			return r;		}		r = old_mgr->apply(old_mgr);		if (r)			return r;	}	if (mgr) {		r = ovl->set_manager(ovl, mgr);		if (r) {			DSSERR("Failed to attach overlay/n");			return r;		}		r = mgr->apply(mgr);		if (r)			return r;	}	return size;}

static int omap_dss_probe(struct platform_device *pdev){	struct omap_dss_platform_data *pdata = pdev->dev.platform_data;	int r;	dss.pdev = pdev;	r = get_dss_clocks();	if (r)		goto fail0;	dss_clk_enable_all_no_ctx();	dss.ctx_id = dss_get_ctx_id();	DSSDBG("initial ctx id %u/n", dss.ctx_id);	r = dss_init();	if (r) {		DSSERR("Failed to initialize DSS/n");		goto fail0;	}#ifdef CONFIG_OMAP2_DSS_RFBI	r = rfbi_init();	if (r) {		DSSERR("Failed to initialize rfbi/n");		goto fail0;	}#endif	r = dpi_init();	if (r) {		DSSERR("Failed to initialize dpi/n");		goto fail0;	}	r = dispc_init();	if (r) {		DSSERR("Failed to initialize dispc/n");		goto fail0;	}#ifdef CONFIG_OMAP2_DSS_VENC	r = venc_init();	if (r) {		DSSERR("Failed to initialize venc/n");		goto fail0;	}#endif	if (cpu_is_omap34xx()) {#ifdef CONFIG_OMAP2_DSS_SDI		r = sdi_init();		if (r) {			DSSERR("Failed to initialize SDI/n");			goto fail0;		}#endif#ifdef CONFIG_OMAP2_DSS_DSI		r = dsi_init();		if (r) {			DSSERR("Failed to initialize DSI/n");			goto fail0;		}#endif	}	initialize_displays(pdata);	r = initialize_sysfs(&pdev->dev);	if (r)		goto fail0;	initialize_overlays(def_disp_name);	dss_clk_disable_all();	return 0;	/* XXX fail correctly */fail0:	return r;}

static int hdmi_power_on_full(struct omap_dss_device *dssdev){	int r;	struct omap_video_timings *p;	struct omap_overlay_manager *mgr = hdmi.output.manager;	struct dss_pll_clock_info hdmi_cinfo = { 0 };	r = hdmi_power_on_core(dssdev);	if (r)		return r;	p = &hdmi.cfg.timings;	DSSDBG("hdmi_power_on x_res= %d y_res = %d/n", p->x_res, p->y_res);	hdmi_pll_compute(&hdmi.pll, p->pixelclock, &hdmi_cinfo);	/* disable and clear irqs */	hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);	hdmi_wp_set_irqstatus(&hdmi.wp,			hdmi_wp_get_irqstatus(&hdmi.wp));	r = dss_pll_enable(&hdmi.pll.pll);	if (r) {		DSSERR("Failed to enable PLL/n");		goto err_pll_enable;	}	r = dss_pll_set_config(&hdmi.pll.pll, &hdmi_cinfo);	if (r) {		DSSERR("Failed to configure PLL/n");		goto err_pll_cfg;	}	r = hdmi_phy_configure(&hdmi.phy, hdmi_cinfo.clkdco,		hdmi_cinfo.clkout[0]);	if (r) {		DSSDBG("Failed to start PHY/n");		goto err_phy_cfg;	}	r = hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_LDOON);	if (r)		goto err_phy_pwr;	hdmi5_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg);	/* bypass TV gamma table */	dispc_enable_gamma_table(0);	/* tv size */	dss_mgr_set_timings(mgr, p);	r = hdmi_wp_video_start(&hdmi.wp);	if (r)		goto err_vid_enable;	/*	 * XXX Seems that on we easily get a flood of sync-lost errors when	 * enabling the output. This seems to be related to the time between	 * HDMI VSYNC and enabling the DISPC output.	 *	 * Testing shows that the sync-lost errors do not happen if we enable	 * the DISPC output very soon after HDMI VBLANK. So wait here for	 * VBLANK to reduce the chances of sync-losts.	 */	hdmi_write_reg(hdmi.wp.base, HDMI_WP_IRQSTATUS, HDMI_IRQ_VIDEO_VSYNC);	while (true) {		u32 v = hdmi_read_reg(hdmi.wp.base, HDMI_WP_IRQSTATUS_RAW);		if (v & HDMI_IRQ_VIDEO_VSYNC)			break;		usleep_range(500, 1000);	}	r = dss_mgr_enable(mgr);	if (r)		goto err_mgr_enable;	hdmi_wp_set_irqenable(&hdmi.wp,			HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT);	return 0;err_mgr_enable:	hdmi_wp_video_stop(&hdmi.wp);err_vid_enable:	hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);err_phy_pwr:err_phy_cfg:err_pll_cfg:	dss_pll_disable(&hdmi.pll.pll);err_pll_enable:	hdmi_power_off_core(dssdev);	return -EIO;}

static int hdmi_power_on_full(struct omap_dss_device *dssdev){	int r;	struct omap_video_timings *p;	struct omap_overlay_manager *mgr = dssdev->output->manager;	unsigned long phy;	r = hdmi_power_on_core(dssdev);	if (r)		return r;	dss_mgr_disable(mgr);	p = &hdmi.ip_data.cfg.timings;	DSSDBG("hdmi_power_on x_res= %d y_res = %d/n", p->x_res, p->y_res);	phy = p->pixel_clock;	hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data);	hdmi.ip_data.ops->video_disable(&hdmi.ip_data);	/* config the PLL and PHY hdmi_set_pll_pwrfirst */	r = hdmi.ip_data.ops->pll_enable(&hdmi.ip_data);	if (r) {		DSSDBG("Failed to lock PLL/n");		goto err_pll_enable;	}	r = hdmi.ip_data.ops->phy_enable(&hdmi.ip_data);	if (r) {		DSSDBG("Failed to start PHY/n");		goto err_phy_enable;	}	hdmi.ip_data.ops->video_configure(&hdmi.ip_data);	/* bypass TV gamma table */	dispc_enable_gamma_table(0);	/* tv size */	dss_mgr_set_timings(mgr, p);	r = hdmi.ip_data.ops->video_enable(&hdmi.ip_data);	if (r)		goto err_vid_enable;	r = dss_mgr_enable(mgr);	if (r)		goto err_mgr_enable;	return 0;err_mgr_enable:	hdmi.ip_data.ops->video_disable(&hdmi.ip_data);err_vid_enable:	hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);err_phy_enable:	hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);err_pll_enable:	hdmi_power_off_core(dssdev);	return -EIO;}